m6502, a 6502 CPU for FPGAs and Tiny Tapeout
Hey HN, Recently built an Apple II emulator and at the same time was getting into Tiny Tapeout and decided it would be cool to build a cycle-accurate 6502 CPU and an MCU for it. It's cycle accurate and the core itself should be 100% compatible with a stock MOS 6502 (would need to still test this though!). Tested on some FPGAs (fomu, ulx3s) and works great, hoping to get it taped out in the upcoming IHP26a shuttle. Also as part of the project I built a bus multiplexer to allow memory/bus access from an RP2040 to work around the limited pin count on Tiny Tapeout. This let's you load up…
What it does
In the maker’s words, at launch
Hey HN, Recently built an Apple II emulator and at the same time was getting into Tiny Tapeout and decided it would be cool to build a cycle-accurate 6502 CPU and an MCU for it. It's cycle accurate and the core itself should be 100% compatible with a stock MOS 6502 (would need to still test this though!). Tested on some FPGAs (fomu, ulx3s) and works great, hoping to get it taped out in the upcoming IHP26a shuttle. Also as part of the project I built a bus multiplexer to allow memory/bus access from an RP2040 to work around the limited pin count on Tiny Tapeout. This let's you load up programs on RP2040 and the CPU can read/write from it.
Does the same job
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Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
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