We built an 8-bit CPU as 2nd year EE students
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
We built an 8-bit CPU as 2nd year EE students launched on June 15, 2026 with 108 votes, #350 of 22,647 launches that month and more than 95% of that year's launches.
In plain words
A team of second-year electrical engineering students designed and built an 8-bit CPU from scratch using Logisim, simulating the hardware entirely with discrete logic gates. The system features a custom 16-instruction Harvard architecture with four general-purpose registers and a hardwired control unit built from AND/OR gates rather than microcode ROM. It uses dual-phase clocking to prevent race conditions and includes a bootstrap control unit for cold-booting. The full design specification and code are available on GitHub.
written from the facts on this page · September 2026
From the sources
8-bit Harvard CPU built from individual logic gates in Logisim-Evolution. - c0rRupT9/STEPLA-1
A complete 8-bit Harvard architecture CPU designed and simulated in Logisim-Evolution, built entirely from individual logic gates down to the gate level. STEPLA-1 is a fully functional 8-bit CPU where every component; registers, decoders, ALU, control unit is built from individual 74-series logic gates. No black box components. Every signal path is visible, traceable, and documented. Unlike EEPROM-based designs, STEPLA-1 uses a fully hardwired control unit a gate-level AND/OR matrix where every control signal is a physical gate whose inputs you can probe with a multimeter. This makes the machine transparent in a way that microcode-based designs cannot be. STEPLA-1 takes a third path:…from github.com
In the maker’s words, at launch
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom…
Does a similar job
all alternatives →- H1Homebrew 16bit CPU from 74HC logic with C compiler and Unix-like OS2023 · sol-1.org · ▲192
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
A nibble-oriented CPU in Verilog to build a scientific calculatorMay 2026 · github.com · ▲119The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
Homemade 32-bit CPU and OS (2015) [video]2016 · youtube.com · ▲253
8-bit CPU simulator in C2020 · github.com · ▲67A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
- IAI Am Making an 8-Bit CPU in Logisim2017 · ▲5
Hey HN, I am making an 8-Bit CPU in Logisim and blogging about it.t's nothing fancy, really simple, unoptimized dumb CPU for sake of learning. I am no electrical engineer, I am just a self-taught dude who has programming as a hobby and wanted to dive deeper into abstractions. So here it is, so far I wrote 2 parts: [links redacted] I welcome any and all critique and feedback, as I can be wrong about everything for sure.
Bit Serial CPU2020 · github.com · ▲99A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial
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