I Am Making an 8-Bit CPU in Logisim

Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…

I built a tiny 8-bit CPU simulator in Python to better understand how computers work at a low level. It visualizes registers, memory, and instructions in real-time, so you can actually see each operation as it happens. You can write simple assembly code and watch how the CPU executes it step by step. The project is mainly for learning and experimentation, but I’d love feedback or ideas for improvement.

A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.

Just wanted to make my first post about something interesting I've been working on for some time. Any ideas/suggestions for new hardware or software I should try out are welcome, though I will only have time for a major overhaul in a month or two where I want to redo and document everything a bit better than how it is currently. Hope this can inspire someone to start their own homelab or give some ideas to already existing ones!

I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…

Hey HN! I made a completely open sourced alternative to Weights and Biases with (insert cringe) blazingly fast performance (yes we use rust and clickhouse) Weights and Biases is super unperformant, their logger blocks user code... logging should not be blocking, yet they got away with it. We do the right thing by being non blocking. Would love any thoughts / feedbacks / roasts etc