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Life & fun · January 17, 2026

E80: an 8-bit CPU in structural VHDL

I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…

E80: an 8-bit CPU in structural VHDL launched on January 17, 2026 with 34 votes, #617 of 14,584 launches that month and more than 95% of that year's launches.

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In plain words

E80 is an 8-bit CPU designed in structural VHDL without high-level abstraction, built entirely from basic logic components like ripple carry adders and flip-flops rather than optimized libraries. It is intended for students and educators who want to understand the underlying hardware principles behind CPU design, as every component is explicitly implemented to mirror what is taught in digital logic courses. The project prioritizes educational clarity over resource efficiency, making it less optimized than commercial soft-cores but more transparent in showing how processors actually work.

written from the facts on this page · September 2026

From the sources

Educational VHDL computer with a single-click toolchain for assembly, simulation, and execution on FPGAs - Stokpan/E80

is a simple von Neumann computer originally developed for my undergraduate thesis as a Papertian Microworld. It provides a textbook-complete instruction set, a toolchain for one-click assembly and simulation, and a pre-configured hardware interface for three low-cost FPGA boards. Where classic microworlds treat their Object‑to‑think‑with as a black box, the E80 CPU is built with structural VHDL and flip‑flops, using ieee.std_logic_1164 only. This allows a student versed in elementary digital logic to understand and modify the Object itself. The implementation's engineering and methodology was presented at PACET 2026 and the paper is available on IEEE Xplore . Operands : n = 8-bit immediate…from github.com

In the maker’s words, at launch

I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn…

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