Life & fun · alternatives · 2026

24 alternatives to E80: an 8-bit CPU in structural VHDL

I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…

E80 is an 8-bit CPU designed in structural VHDL without high-level abstraction, built entirely from basic logic components like ripple carry adders and flip-flops rather than optimized libraries. It is intended for… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes.

1
We built an 8-bit CPU as 2nd year EE students▲108
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com · its alternatives →
2
Bit Serial CPU▲99
A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial
2020 · github.com · its alternatives →
3
8-bit CPU simulator in C▲67
A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
2020 · github.com · its alternatives →
4
I built a hardware processor that runs Python▲983
Hi everyone, I built PyXL — a hardware processor that executes a custom assembly generated from Python programs, without using a traditional interpreter or virtual machine. It compiles Python -> CPython Bytecode -> Instruction set designed for direct hardware execution. I’m sharing an early benchmark: a GPIO test where PyXL achieves a 480ns round-trip toggle — compared to 14-25 micro seconds on a MicroPython Pyboard - even though PyXL runs at a lower clock (100MHz vs. 168MHz). The design is stack-based, fully pipelined, and preserves Python's dynamic typing without static type restrictions.…
2025 · runpyxl.com · its alternatives →
5AD
Atopile – Design circuit boards with code▲595
Hey HN! We are the founders of atopile. We’re building a tool to describe electronics with code. Here is a quick demo: https://youtu.be/7-Q0XVpfW3Y Could you imagine the pain of building an entire software product using only assembly code? That’s about how we felt designing hardware. We don’t currently have good ways to describe what we need, reuse existing designs and compile that description down to a product. We started atopile to fix this. atopile is an open-source language and toolchain to describe circuits with code. The compiler is here:…
2024 · its alternatives →
6
SHDL – A minimal hardware description language built from logic gates▲48
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…
Jan 2026 · github.com · its alternatives →
7AR
A RISC-V core in Racket▲122
2021 · guillaume.baierouge.fr · its alternatives →
8
Z80-μLM, a 'Conversational AI' That Fits in 40KB▲514
How small can a language model be while still doing something useful? I wanted to find out, and had some spare time over the holidays. Z80-μLM is a character-level language model with 2-bit quantized weights ({-2,-1,0,+1}) that runs on a Z80 with 64KB RAM. The entire thing: inference, weights, chat UI, it all fits in a 40KB .COM file that you can run in a CP/M emulator and hopefully even real hardware! It won't write your emails, but it can be trained to play a stripped down version of 20 Questions, and is sometimes able to maintain the illusion of having simple but terse conversations…
Dec 2025 · github.com · its alternatives →
9H1
Homebrew 16bit CPU from 74HC logic with C compiler and Unix-like OS▲192
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
2023 · sol-1.org · its alternatives →
10
A nibble-oriented CPU in Verilog to build a scientific calculator▲119
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com · its alternatives →
11
I built a handheld CHIP-8 game console to teach myself embedded systems▲128
A while back I wrote a CHIP-8 emulator (which is considered the Hello, World! of emulators and is more accurately a virtual machine since historically CHIP-8 was an interpreted language running on top of the COSMAC VIP to make game programming easier). But a few months ago I got really interested in embedded software, so decided it would be neat to port my emulator to a STM32 MCU and design a console around it as a learning experience, since CHIP-8 never existed as a physical system. I didn't know much about embedded software when I began, and even less about electronics, but I managed to…
2022 · github.com · its alternatives →
12
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
13
Homemade 32-bit CPU and OS (2015) [video]▲253
2016 · youtube.com · its alternatives →
14
I built an 8-bit CPU simulator in Python from scratch▲72
I built a tiny 8-bit CPU simulator in Python to better understand how computers work at a low level. It visualizes registers, memory, and instructions in real-time, so you can actually see each operation as it happens. You can write simple assembly code and watch how the CPU executes it step by step. The project is mainly for learning and experimentation, but I’d love feedback or ideas for improvement.
Oct 2025 · github.com · its alternatives →
15
RISC-V core written in 600 lines of C89▲190
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
16LA
L88 – A Local RAG System on 8GB VRAM (Need Architecture Feedback)▲12
Hey everyone, I’ve been working on a project called L88 — a local RAG system that I initially focused on UI/UX for, so the retrieval and model architecture still need proper refinement. Repo: https://github.com/Hundred-Trillion/L88-Full I’m running this on 8GB VRAM and a strong CPU (128GB RAM). Embeddings and preprocessing run on CPU, and the main model runs on GPU. One limitation I ran into is that my evaluator and generator LLM ended up being the same model due to compute constraints, which defeats the purpose of evaluation. I’d really appreciate feedback on:…
Feb 2026 · its alternatives →
17
An AVR based 8-bit Microcomputer▲43
DAN64 is a open software and open hardware project to build an 8-bit microcomputer using an AVR microcontroller.
2015 · usebox.net · its alternatives →
18
8bitworkshop IDE for Atari 2600▲289
Learn how classic game hardware worked. Write code and see it run instantly.
2016 · 8bitworkshop.com · its alternatives →
19
A 16-bit Forth machine written in VHDL▲80
Yet Another Forth Core... Contribute to inforichland/yafc development by creating an account on GitHub.
2014 · github.com · its alternatives →
20
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
21
A small virtual machine written in C▲212
"interesting" VM in C. Let's see how this goes. Contribute to tekknolagi/carp development by creating an account on GitHub.
2014 · github.com · its alternatives →
22
CHIP-8 console implemented in FPGA▲120
CHIP-8 console on FPGA. Contribute to pwmarcz/fpga-chip8 development by creating an account on GitHub.
2018 · github.com · its alternatives →
23
I'm making a dynamic language in Rust▲184
An implementation of a dynamic programming language in Rust. Includes: Parser/Compiler, REPL, Virtual Machine, Bytecode Disassembler This started out as a learning project to teach myself Rust. It has grown into a decently substantial piece of software and I've learned quite a bit in the process! Some neat things: + A garbage collector that can store dynamically sized types without any double-indirection (i.e. I have my own Box implementation with manual alloc/dealloc) + The smart pointer used to reference GCed data is a thin pointer. The ptr metadata needed for DSTs is stored in…
2022 · github.com · its alternatives →
24
A hash array-mapped trie implementation in C▲171
Long-simmering side project that is finally ready to see the light. HAMTs are a cool persistent data structure and implementing one has been a lot of fun. Beyond the code, there is likely some value in the extensive and largely complete implementation docs; basic benchmarks are linked in the README, too. Kind of aiming to be "the libavl for HAMTs". That is obviously a high and aspirational bar but a distinct possibility if it stirs up a little interest and/or contribution. Anyways, it's time for this to go out, collect feedback and maybe even some use outside of toy projects. Let me…
2023 · github.com · its alternatives →

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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →