Alternatives
Products that do what Homebrew 16bit CPU from 74HC logic with C compiler and Unix-like OS does
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
- 1WB
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com
- 2OS
Hi HN, I built a specialized inference engine for running 4-bit Gemma 4 26B-A4B-IT on any M-series Mac using about 2 GB of RAM. It is called TurboFieldfare and is written in Swift and Metal. I have always adored on-device AI. It feels like magic that you can run a powerful NN on your Mac or iPhone. So I wanted to push the limits a bit and run a model whose weights don’t fit in memory. The model’s 4-bit quantized weights occupy roughly 14 GB, which makes running it with conventional inference tools almost impossible on an 8 GB or even 16 GB Mac once the OS, applications, and KV cache are…
Jul 2026 · github.com
- 3AN
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com
- 4H6Homebrew 6.0.0▲1,481
Today, I’m proud to announce Homebrew 6.0.0. The most significant changes since 5.1.0 are a new tap trust security mechanism, the new faster, smaller, default internal Homebrew JSON API, sandboxing on Linux, better defaults informed by our user survey, many brew bundle improvements, improved performance and initial support for macOS 27 (Golden Gate). Happy to discuss any questions here!
Jun 2026 · brew.sh
- 5HT
2017 · blog.klipse.tech
- 6BA
I am a Dutch high school student and last year I had to do a large project of my own choice. Together with two other guys I decided to do a project about digital logic. We had an ambitious plan: building an 8-bits computer. At that time I started learning programming and I already knew some HTML and CSS. So we decided to not build a physical computer, but one running in a self-built simulator. I was going to build the simulator, the other guys took care of the computer. I was hard, our school hadn't taught us anything about computers and programming so we had to learn everything ourselves.…
2017
- 7AC
2020 · github.com
- 8A1
2014 · github.com
- 9SF
5 years ago, I made a derivative of SAP-1 (mainly inspired by Ben Eater) on breadboard with few improvement and called it MSAP-1 (https://github.com/mehrantsi/MSAP-1) I made my own very primitive Assembly language and a simple Arduino programmer (https://github.com/mehrantsi/8-bit_CPU_Programmer) where I could load my programs onto MSAP-1 and even Debug them (https://github.com/mehrantsi/8-bit_CPU_Debugger). After that I started worked on the second version of it (https://github.com/mehrantsi/MSAP-2) by adding…
Jul 2026 · msap2.mehran.dk
- 10SH
2018 · github.com
- 11AT
A 3.16M-parameter INT4 transformer running entirely in the on-chip memory of a Xilinx Kria KV260. Zero DRAM in the token loop, 59,965 tok/s on the fabric, bit-exact. Chat with it live.
27d ago · mikeayles.com
- 12NNibble▲102
An attempt at a single pass LLVM frontend in ~3000 lines of C without external dependencies, malloc, or an AST. Included are some graphical examples. The IR isn't perfect, and the README touches on one particular downfall
May 2026 · github.com
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- 15RV
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
Mar 2026 · github.com
- 16IR
The Emotion Engine has 32 MB of RAM total, so the trick is streaming weights from CD-ROM one matrix at a time during the forward pass — only activations, KV cache and embeddings live in RAM. This means models bigger than the RAM can still run, they just read more from disc. Had to build a custom quantized format (PSNT), hack endianness, write a tokenizer pipeline, and most of the PS2 SDK from scratch (releasing that separately). The model itself is also custom — a 10M param Llama-style architecture I trained specifically for this. And it works. On real hardware.
Mar 2026 · github.com
- 17RA
Hi, I've made a Dis virtual machine and Limbo programming language compiler (called RiceVM) in Rust. It can run Dis bytecode (for example, Inferno OS applications), compile Limbo programs, and includes a fairly complete runtime with garbage collection, concurrency features, and many of the standard modules from Inferno OS's original implementation. The project is still in an early stage, but if you're interested in learning more about RiceVM or trying it out, you can check out the links below: Project's GitHub repo: https://github.com/habedi/ricevm RiceVM documentation:…
Apr 2026
- 18
I built a 16-bit CPU simulator that runs entirely in the browser. You can write assembly, run it, or step through it one instruction at a time while watching what happens inside the CPU. It shows the registers, memory, flags, ALU, buses, and datapath as the program executes. You can also set breakpoints, inspect execution cycles, replay previous cycles, and try some example programs. I built this because I wanted CPU architecture to feel more tangible. Reading about fetch, decode, registers, buses, and the ALU is one thing. Watching an instruction actually move through the CPU is much more…
24d ago · coretrace.srianjaneyam.me
- 19WS
Jul 2026 · risingedge.pro
- 20
I built a specialized package of DeepSeek V4 Flash 0731 (originally 284B total parameters, 13B active), preserving reasoning, tool calling and coding capabilities: https://huggingface.co/steadfastgaze/DeepSeek-V4-Flash-0731-... I let it write a minimal C compiler targeting ARM64, then test the result with Fibonacci and FizzBuzz programs, and it succeeded in less than 1 hour, with the full recording at: https://youtu.be/XiwSilmV8B0 You can run it on Silicon Macs with my engine https://github.com/steadfastgaze/MoEspresso, while one of the…
21d ago · huggingface.co
- 21IA
Hey HN, I am making an 8-Bit CPU in Logisim and blogging about it.t's nothing fancy, really simple, unoptimized dumb CPU for sake of learning. I am no electrical engineer, I am just a self-taught dude who has programming as a hobby and wanted to dive deeper into abstractions. So here it is, so far I wrote 2 parts: [links redacted] I welcome any and all critique and feedback, as I can be wrong about everything for sure.
2017
- 22DO
Disclaimer, I have not yet placed the order. But JLCPCB have so far excepted all files and config so I have 1 more button to press. If anyone see some obvious mistake please send feedback. This project grew out of curiosity. Loved the https://monster6502.com/ project but that is on another level. Here I tried to stay "reasonable" and added a Raspberry Pico 2 W on the back to drive it all. But also, was curious if Claude could pull this off. Guess I will have to place that order to call the cards.
Jul 2026 · epatel.github.io
- 23RG
I wanted to know how fast a 26B mixture-of-experts model could run on a desktop CPU with no GPU. Got ~40 tok/s single-stream (lossless) and ~124 batched. The surprising part was the byte budget: for this model you compress the output head (32% of per-token bytes), not the experts (16%). The writeup has the bandwidth roofline and the dead-ends; the repo has the reproducible recipe. Happy to answer questions. Repo: https://github.com/arun-prasath2005/gemma4-cpu-moe
Jun 2026 · apeg.dev
- 24IM
This is a personal project I've been working on and off for the past few years. It's a set of tools that have allowed me to prototype quickly small (and increasingly bigger) kernels, and create userspace programs to interact with them. Supports riscv64, amd64 and i386. The intel port has been tested and used on real hardware, from big dual-socket Xeon machines to an old X220. It is all C, I have plan to make rust bindings for the kernel library. But again, they're plans at this stage. Porting to new architectures is relatively simple, a basic port to riscv took me a couple of weeks of…
2024 · github.com
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