A nibble-oriented CPU in Verilog to build a scientific calculator
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
A nibble-oriented CPU in Verilog to build a scientific calculator launched on May 15, 2026 with 119 votes, #238 of 20,538 launches that month and more than 95% of that year's launches.
In plain words
This project is a custom CPU designed in Verilog specifically for building scientific calculators, inspired by how HP calculators operated at the hardware level. The CPU uses a nibble-oriented architecture (4-bit data width) with BCD number storage, making it naturally suited for decimal calculations rather than forcing them through byte-oriented processors. It includes a Harvard architecture, custom instruction set, hardware stack protection, and CORDIC algorithms for trigonometric functions. The project provides a two-pass assembler, simulation framework compatible with multiple platforms including WebAssembly, and supporting documentation for understanding calculator design fundamentals.
written from the facts on this page · September 2026
From the sources
From FPGA Gates to Scientific Calculator. Contribute to gdevic/FPGA-Calculator development by creating an account on GitHub.
This project implements a fully functional scientific calculator in hardware using an FPGA. It includes a custom soft CPU, microcode firmware, and supporting tools. # From WSL2 cd /mnt/c/Projects/FPGA-Calculator/verilog make qt Then open Qt/Calculator.pro in Qt Creator and build for "Desktop Qt MSVC2022 64 Bit". Verilator runs in WSL2 (Windows Subsystem for Linux). The project source files reside on a Windows partition and are accessed from WSL2. # Install prerequisites sudo apt-get install build-essential autoconf flex libfl-dev bison # Clone and build Verilator git clone https://github.com/verilator/verilator cd verilator git checkout v5.042 # For Desktop, or v4.228 for WebAssembly…from github.com
In the maker’s words, at launch
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80…
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