Alternatives
Products that do what A nibble-oriented CPU in Verilog to build a scientific calculator does
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
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Hi HN, I built a specialized inference engine for running 4-bit Gemma 4 26B-A4B-IT on any M-series Mac using about 2 GB of RAM. It is called TurboFieldfare and is written in Swift and Metal. I have always adored on-device AI. It feels like magic that you can run a powerful NN on your Mac or iPhone. So I wanted to push the limits a bit and run a model whose weights don’t fit in memory. The model’s 4-bit quantized weights occupy roughly 14 GB, which makes running it with conventional inference tools almost impossible on an 8 GB or even 16 GB Mac once the OS, applications, and KV cache are…
Jul 2026 · github.com
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Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com
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2016 · knightos.org
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2017 · insect.sh
- 6KR
I discovered that in LLM inference, keys and values in the KV cache have very different quantization sensitivities. Keys need higher precision than values to maintain quality. I patched llama.cpp to enable different bit-widths for keys vs. values on Apple Silicon. The results are surprising: - K8V4 (8-bit keys, 4-bit values): 59% memory reduction with only 0.86% perplexity loss - K4V8 (4-bit keys, 8-bit values): 59% memory reduction but 6.06% perplexity loss - The configurations use the same number of bits, but K8V4 is 7× better for quality This means you can run LLMs with 2-3× longer…
2025 · github.com
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2021 · mkhan45.github.io
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A 3.16M-parameter INT4 transformer running entirely in the on-chip memory of a Xilinx Kria KV260. Zero DRAM in the token loop, 59,965 tok/s on the fabric, bit-exact. Chat with it live.
27d ago · mikeayles.com
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We wrote our inference engine on Rust, it is faster than llama cpp in all of the use cases. Your feedback is very welcomed. Written from scratch with idea that you can add support of any kernel and platform.
2025 · github.com
- 10IB
I built a tiny 8-bit CPU simulator in Python to better understand how computers work at a low level. It visualizes registers, memory, and instructions in real-time, so you can actually see each operation as it happens. You can write simple assembly code and watch how the CPU executes it step by step. The project is mainly for learning and experimentation, but I’d love feedback or ideas for improvement.
Oct 2025 · github.com
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2021 · kalk.strct.net
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Aug 2026 · github.com
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We wanted to do something very challenging to prove to ourselves that we can do anything we put our mind to. The reasoning for why we chose to build a toy TPU specifically is fairly simple: - Building a chip for ML workloads seemed cool - There was no well-documented open source repo for an ML accelerator that performed both inference and training None of us have real professional experience in hardware design, which, in a way, made the TPU even more appealing since we weren't able to estimate exactly how difficult it would be. As we worked on the initial stages of this project, we…
2025 · tinytpu.com
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https://github.com/siraben/ti84-forth Hi HN! For the past year I've been getting into programming in Z80 assembly (especially for the TI-84+). More recently I've been learning about the Forth programming language and after a lot of searching online (in vain) for a Forth interpreter for the TI-84, I decided to write one myself. It's been fun demoing this to others, because it's a very unexpected use of a calculator. It's my largest project to date, and I'm interested to know what the HN community thinks, please feel free to critique my code! -- Ben
2018
- 15IB
You know that old TI calculator you used in high school, then put in a box and forgot about? Have you ever wished you had an operating system for your calculator with preemptive multitasking, dynamic memory management, a tree filesystem conforming to the FHS, and all the comforts of Unix? Well, good news: that's totally a thing that exists. I've been working on my kernel for about three and a half years now and I'm looking for new contributors to help out. It's written entirely in z80 assembly, and it's both challenging and fun to work on. There's an IRC channel for contributors or people…
2014
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2020 · github.com
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2015 · github.com
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Wrote this to learn more about the `chumsky` parser combinator library, rustyline, and the `ariadne` error reporting crate. Such a nice DX combo for writing new languages. Still a work in progress, but I thought I'd share :)
2025 · github.com
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2020 · github.com
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I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com
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I wanted to know how fast a 26B mixture-of-experts model could run on a desktop CPU with no GPU. Got ~40 tok/s single-stream (lossless) and ~124 batched. The surprising part was the byte budget: for this model you compress the output head (32% of per-token bytes), not the experts (16%). The writeup has the bandwidth roofline and the dead-ends; the repo has the reproducible recipe. Happy to answer questions. Repo: https://github.com/arun-prasath2005/gemma4-cpu-moe
Jun 2026 · apeg.dev
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Github: https://github.com/errorcodezero/turbine
2025 · errorcodezero.dev
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Hi HN friends, we're Nima (nimabanai) and Craig (cbschind) from Assemble Labs (https://assemblelabs.co) building the hardware context layer for AI to help you write better firmware faster. We’ve built an MCP server that plugs into any AI tool you’re using (Cursor, Claude Code, Gemini, etc.) and brings complete hardware context (schematics, datasheets, etc.) to your existing environment (new app fatigue is real...) with accuracy and in real time. Our goal is to make writing and debugging firmware on custom hardware faster and easier. Try out the free beta release:…
Oct 2025
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