Life & fun · alternatives · 2026

24 alternatives to Bit Serial CPU

A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial

Bit Serial CPU is an educational processor implementation available on GitHub. It demonstrates how central processing units work at a fundamental level by building a functional CPU with serial bit operations. Designed… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. Bit Serial CPU launched in 2020; newer entries below may have overtaken it.

1
8-bit CPU simulator in C▲67
A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
2020 · github.com · its alternatives →
2
I built an 8-bit CPU simulator in Python from scratch▲72
I built a tiny 8-bit CPU simulator in Python to better understand how computers work at a low level. It visualizes registers, memory, and instructions in real-time, so you can actually see each operation as it happens. You can write simple assembly code and watch how the CPU executes it step by step. The project is mainly for learning and experimentation, but I’d love feedback or ideas for improvement.
Oct 2025 · github.com · its alternatives →
3
H2 Forth CPU▲120
A Forth CPU and System on a Chip, based on the J1, written in VHDL - howerj/forth-cpu
2019 · github.com · its alternatives →
4
We built an 8-bit CPU as 2nd year EE students▲108
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com · its alternatives →
5H1
Homebrew 16bit CPU from 74HC logic with C compiler and Unix-like OS▲192
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
2023 · sol-1.org · its alternatives →
6
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
7
E80: an 8-bit CPU in structural VHDL▲34
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com · its alternatives →
8
RISC-V core written in 600 lines of C89▲190
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
9
CPU simulator in 60 lines of code▲60
Simple CPU model written in 60 lines of C with 8 registers and basic instructions - wkoszek/cpu60
2015 · github.com · its alternatives →
10
A small virtual machine written in C▲212
"interesting" VM in C. Let's see how this goes. Contribute to tekknolagi/carp development by creating an account on GitHub.
2014 · github.com · its alternatives →
11
Homemade 32-bit CPU and OS (2015) [video]▲253
2016 · youtube.com · its alternatives →
12
A 16-bit Forth machine written in VHDL▲80
Yet Another Forth Core... Contribute to inforichland/yafc development by creating an account on GitHub.
2014 · github.com · its alternatives →
13
I wrote my own RTS game engine in C▲1,102
An OpenGL RTS game engine written in C. Contribute to eduard-permyakov/permafrost-engine development by creating an account on GitHub.
2021 · github.com · its alternatives →
14
I built a hardware processor that runs Python▲983
Hi everyone, I built PyXL — a hardware processor that executes a custom assembly generated from Python programs, without using a traditional interpreter or virtual machine. It compiles Python -> CPython Bytecode -> Instruction set designed for direct hardware execution. I’m sharing an early benchmark: a GPIO test where PyXL achieves a 480ns round-trip toggle — compared to 14-25 micro seconds on a MicroPython Pyboard - even though PyXL runs at a lower clock (100MHz vs. 168MHz). The design is stack-based, fully pipelined, and preserves Python's dynamic typing without static type restrictions.…
2025 · runpyxl.com · its alternatives →
15
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
16
SHDL – A minimal hardware description language built from logic gates▲48
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…
Jan 2026 · github.com · its alternatives →
17BA
BOOLR, a digital logic simulator▲78
I am a Dutch high school student and last year I had to do a large project of my own choice. Together with two other guys I decided to do a project about digital logic. We had an ambitious plan: building an 8-bits computer. At that time I started learning programming and I already knew some HTML and CSS. So we decided to not build a physical computer, but one running in a self-built simulator. I was going to build the simulator, the other guys took care of the computer. I was hard, our school hadn't taught us anything about computers and programming so we had to learn everything ourselves.…
2017 · its alternatives →
18LC
Learn C and its lower levels interactively, in the browser▲356
I made a simple virtual machine that runs C in the browser.This project is made as an experiment to see if C can be learned easier if the lower level is covered in paralel. Sandbox: https://vasyop.github.io/miniC-hosting Tutorial part 1: https://vasyop.github.io/miniC-hosting/?0 More info: https://github.com/vasyop/miniC-hosting/blob/master/README.md Please support this project: https://github.com/vasyop/miniC-hosting/blob/master/support.md
2019 · its alternatives →
19
Low-Level Academy, an explorable systems programming course▲419
Introduction to UDP: sockets, frames, and data encoding. We build a Rust client for a simple name server that converts domain names into IP addresses.
2020 · lowlvl.org · its alternatives →
20AR
A RISC-V core in Racket▲122
2021 · guillaume.baierouge.fr · its alternatives →
21
Write, simulate and synthesize VHDL/Verilog in the browser▲19
Learn digital hardware design in the browser: write VHDL and SystemVerilog, simulate, read waveforms, and synthesize to a netlist. No installation required.
Jul 2026 · risingedge.pro · its alternatives →
22
A toy bootloader written in C++▲64
Yes, this includes the MBR and partition boot sector. The partition table is modeled as a class hierarchy. Second stage loads a kernel from a FAT32 file. I'm normally a C programmer, but for a work project, I recently revisited C++, a language that I had an on-again-off-again relationship over the years. I did this as a fun training exercise on the side to get familiar with the language again, but obsessed a bit and kind of overshot the target. I thought the result might be of interest to someone.
2023 · github.com · its alternatives →
23
Simple virtual machine, assembler, and C compiler▲99
simple virtual machine and assembler. Contribute to ronsoros/rvm development by creating an account on GitHub.
2016 · github.com · its alternatives →
24
8bitworkshop IDE for Atari 2600▲289
Learn how classic game hardware worked. Write code and see it run instantly.
2016 · 8bitworkshop.com · its alternatives →

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