Minimax – A Compressed-First, Microcoded RISC-V CPU
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
Minimax – A Compressed-First, Microcoded RISC-V CPU launched on November 1, 2022 with 171 votes, #184 of 3,471 launches that month and more than 95% of that year's launches. The site was still online in September 2026, 3 years on.
In plain words
Minimax is an experimental RISC-V CPU implementation that prioritizes the compressed instruction set (RVC) as its primary execution format rather than treating it as an add-on. Instead of pre-decoding RVC instructions into standard 32-bit equivalents, Minimax executes them directly and handles other RV32I instructions through a microcode layer. The project explores whether this architecture yields simplifications compared to traditional RV32I cores. While it passes basic tests, it remains experimental and users should exercise caution before relying on it for production use.
written from the facts on this page · September 2026
From the sources
Minimax: a Compressed-First, Microcoded RISC-V CPU - gsmecher/minimax
In the maker’s words, at launch
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to…
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