A pipelined RISC-V processor written in VHDL
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
A pipelined RISC-V processor written in VHDL launched on July 28, 2015 with 65 votes, #1,046 of 4,208 launches that month and more than 95% of that year's launches. The site was still online in September 2026, 11 years on.
In plain words
This is a pipelined RISC-V processor implementation written in VHDL, designed for developers and hardware engineers working with processor design and RISC-V architecture. The project is hosted on GitHub and welcomes community contributions. It provides a complete pipelined processor design that can be used for educational purposes, research, or as a foundation for custom processor development.
written from the facts on this page · September 2026
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