Dev tools · alternatives · 2026

24 alternatives to A pipelined RISC-V processor written in VHDL

A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.

This is a pipelined RISC-V processor implementation written in VHDL, designed for developers and hardware engineers working with processor design and RISC-V architecture. The project is hosted on GitHub and welcomes… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. A pipelined RISC-V processor written in VHDL launched in 2015; newer entries below may have overtaken it.

1
RISC-V core written in 600 lines of C89▲190
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
2AR
A RISC-V core in Racket▲122
2021 · guillaume.baierouge.fr · its alternatives →
3
I built a hardware processor that runs Python▲983
Hi everyone, I built PyXL — a hardware processor that executes a custom assembly generated from Python programs, without using a traditional interpreter or virtual machine. It compiles Python -> CPython Bytecode -> Instruction set designed for direct hardware execution. I’m sharing an early benchmark: a GPIO test where PyXL achieves a 480ns round-trip toggle — compared to 14-25 micro seconds on a MicroPython Pyboard - even though PyXL runs at a lower clock (100MHz vs. 168MHz). The design is stack-based, fully pipelined, and preserves Python's dynamic typing without static type restrictions.…
2025 · runpyxl.com · its alternatives →
4
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
5
Bit Serial CPU▲99
A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial
2020 · github.com · its alternatives →
6
IDE for Learning RISC-V▲105
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
7
A small virtual machine written in C▲212
"interesting" VM in C. Let's see how this goes. Contribute to tekknolagi/carp development by creating an account on GitHub.
2014 · github.com · its alternatives →
8
H2 Forth CPU▲120
A Forth CPU and System on a Chip, based on the J1, written in VHDL - howerj/forth-cpu
2019 · github.com · its alternatives →
9AD
Atopile – Design circuit boards with code▲595
Hey HN! We are the founders of atopile. We’re building a tool to describe electronics with code. Here is a quick demo: https://youtu.be/7-Q0XVpfW3Y Could you imagine the pain of building an entire software product using only assembly code? That’s about how we felt designing hardware. We don’t currently have good ways to describe what we need, reuse existing designs and compile that description down to a product. We started atopile to fix this. atopile is an open-source language and toolchain to describe circuits with code. The compiler is here:…
2024 · its alternatives →
10
A work-in-progress C compiler from scratch▲159
Programming language that compiles into a x86 ELF executable. - riicchhaarrd/ocean
2021 · github.com · its alternatives →
11
Instill VDP▲130
Open source unstructured data ETL for AI first applications
2024 · instill-ai.com · its alternatives →
12
RISC-V assembly tabletop board game (hack your opponent)▲400
I made this game to teach my daughter how buffer overflows work. I want her to look at programs as things she can change, and make them do whatever she wants. Building your exploit in memory and jumping to it feels so cool. I hope this game teaches kids and programmers (who seem to have forgotten what computers actually are) that its quite fun to mess with programs. We used to have that excitement few years ago, just break into softice and change a branch into a nop and ignore the serial number check, or go to a different game level because this one is too annoying. While working on the game…
2023 · punkx.org · its alternatives →
13
Write, simulate and synthesize VHDL/Verilog in the browser▲19
Learn digital hardware design in the browser: write VHDL and SystemVerilog, simulate, read waveforms, and synthesize to a netlist. No installation required.
Jul 2026 · risingedge.pro · its alternatives →
14
A 16-bit Forth machine written in VHDL▲80
Yet Another Forth Core... Contribute to inforichland/yafc development by creating an account on GitHub.
2014 · github.com · its alternatives →
15
I wrote an OS in 1000 lines of Zig▲151
A minimal RISC-V 32-bit OS written in Zig. Contribute to botirkhaltaev/pico-os development by creating an account on GitHub.
2025 · github.com · its alternatives →
16
E80: an 8-bit CPU in structural VHDL▲34
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com · its alternatives →
17
Chili. Rust port of Spice, a low-overhead parallelization library▲233
Rust port of Spice, a low-overhead parallelization library - dragostis/chili
2024 · github.com · its alternatives →
18
Sub-millisecond VM sandboxes using CoW memory forking▲311
I wanted to see how fast an isolated code sandbox could start if I never had to boot a fresh VM. So instead of launching a new microVM per execution, I boot Firecracker once with Python and numpy already loaded, then snapshot the full VM state. Every execution after that creates a new KVM VM backed by a `MAP_PRIVATE` mapping of the snapshot memory, so Linux gives me copy-on-write pages automatically. That means each sandbox starts from an already-running Python process inside a real VM, runs the code, and exits. These are real KVM VMs, not containers: separate guest kernel, separate guest…
Mar 2026 · github.com · its alternatives →
19
RISC-V disassembler in 200 lines of C▲29
A minimal RISC-V RV32I disassembler. Contribute to andportnoy/riscv-disassembler development by creating an account on GitHub.
2020 · github.com · its alternatives →
20
Open-source, configurable HDMI output for FPGAs▲195
Send video/audio over HDMI on an FPGA. Contribute to hdl-util/hdmi development by creating an account on GitHub.
2020 · github.com · its alternatives →
21
A Project Oberon System version running on RISC-V instead of RISC-5▲121
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
Aug 2026 · github.com · its alternatives →
22
Pipelex – Declarative language for repeatable AI workflows▲122
We’re Robin, Louis, and Thomas. Pipelex is a DSL and a Python runtime for repeatable AI workflows. Think Dockerfile/SQL for multi-step LLM pipelines: you declare steps and interfaces; any model/provider can fill them. Why this instead of yet another workflow builder? - Declarative, not glue code: you state what to do; the runtime figures out how. - Agent-first: each step carries natural-language context (purpose, inputs/outputs with meaning) so LLMs can follow, audit, and optimize. Our MCP server enables agents to run pipelines but also to build new pipelines on demand. - Open…
Oct 2025 · github.com · its alternatives →
23
Confidential computing for high-assurance RISC-V embedded systems▲103
Dear HN community! Looking forward to hearing your feedback on ACE (assured confidential execution), technology that implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware. We target high-assurance systems that can benefit from compartmentalization and hardware-backed isolation. The key ingredient called security monitor (firmware) is implemented in Rust. The formal specification is defined as annotations directly in code and gets translated to Coq using RefinedRust automation. ACE design is now part of the…
2025 · github.com · its alternatives →
24
I built a RISC-V emulator that runs DOOM▲50
Demo: https://www.youtube.com/watch?v=f5uygzEmdLw Hi HN, I built a RISC-V emulator that implements the RV32IM instruction set and a minimal syscall interface to run DOOM. A few weeks ago, I got my first output with a simple hello world assembly program. Since then I have been working tirelessly to get DOOM to run. I needed to figure out how to run C programs first, and came across newlib, which allows the underlying environment to implement the syscall stubs one by one until the programs run. I have also added ELF loading, but currently only a single `PT_LOAD` segment is…
May 2026 · github.com · its alternatives →

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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →