Dev tools · alternatives · 2026

24 alternatives to A Project Oberon System version running on RISC-V instead of RISC-5

Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32

This is a modified Project Oberon System that runs on RISC-V (RV32) architecture instead of the original RISC-5. The system has been migrated from Oberon 07 to Oberon 90 and uses the OP2 compiler with a RISC-V backend.… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes.

1
Oberon System 3 runs natively on Raspberry Pi 3 (with ready SD card)▲245
This is a version based on v2.3.7 running on emulated PC i386, native Raspi Model 3b and Zero 2, and eventually Olimex ESP32-P4-PC, using existing bootloaders instead of Oberon0 - Releases · rochus-keller/OberonSystem3Native
Apr 2026 · github.com · its alternatives →
2
IDE for Learning RISC-V▲105
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
3
RISC-V core written in 600 lines of C89▲190
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
4
Getting GLM 5.2 running on my slow computer▲937
A few days ago I found myself trying out GLM 5.2 and was really positively impressed. The capabilities and security I was getting from this LLM are similar to those I've gotten from models like Claude or GPT, and this really surprised me. But then I thought, "I wonder how it would work on a normal computer like mine," and above all, "I wonder if it would work without going into OOM on a computer like mine." So I started working with the help of agents to test this possibility. I started converting the model to int4, understanding MTP usage, and if possible implementing DSA for long context.…
Jul 2026 · github.com · its alternatives →
5
C++17 RISC-V RV32GC / RV64GC userspace emulator library▲31
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2020 · github.com · its alternatives →
6
v8-riscv — Port of JavaScript V8 engine to RISC-V▲123
Port of Google v8 engine to RISC-V. Contribute to riscv-collab/v8 development by creating an account on GitHub.
2021 · github.com · its alternatives →
7
Libriscv – RISC-V userspace emulator library▲40
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
8
I built a RISC-V emulator that runs DOOM▲50
Demo: https://www.youtube.com/watch?v=f5uygzEmdLw Hi HN, I built a RISC-V emulator that implements the RV32IM instruction set and a minimal syscall interface to run DOOM. A few weeks ago, I got my first output with a simple hello world assembly program. Since then I have been working tirelessly to get DOOM to run. I needed to figure out how to run C programs first, and came across newlib, which allows the underlying environment to implement the syscall stubs one by one until the programs run. I have also added ELF loading, but currently only a single `PT_LOAD` segment is…
May 2026 · github.com · its alternatives →
9AR
A RISC-V core in Racket▲122
2021 · guillaume.baierouge.fr · its alternatives →
10
Porting xv6 to HiFive Unmatched board▲26
Hi HN, I ported the teaching OS xv6-riscv to HiFive Unmatched and got it running on real hardware, including passing usertests. I've been self-studying OS internals using the MIT 6.1810 materials. After finishing most of the labs, I was eager to see what it's like to run the OS on bare metal, rather than QEMU. The Unmatched may not have the latest RISC-V features, but it's well-documented, and the Rev B release has made it more affordable, which makes it a good learning platform. The porting process involved several interesting challenges: - Hardware Quirks: Handling things like enabling…
Jan 2026 · github.com · its alternatives →
11
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
12
New RISC-V emulator for Computer Science education▲71
Just released EGG, an emulator created for teaching Assembly and microprocessors (designed to suit the needs of the Microprocessors classes, at Universidade Federal do Paraná, Brazil). The emulator will support multiple architetures in the future, but currently only RISC-V is implemented.
2024 · github.com · its alternatives →
13
A cross-platform version of the ETH Oberon System 3▲6
A cross-platform version of the ETH Oberon System 3 compatible with the Oberon+ compiler and IDE - rochus-keller/OberonSystem3
2023 · github.com · its alternatives →
14
A small virtual machine written in C▲212
"interesting" VM in C. Let's see how this goes. Contribute to tekknolagi/carp development by creating an account on GitHub.
2014 · github.com · its alternatives →
15
RISC-V assembly tabletop board game (hack your opponent)▲400
I made this game to teach my daughter how buffer overflows work. I want her to look at programs as things she can change, and make them do whatever she wants. Building your exploit in memory and jumping to it feels so cool. I hope this game teaches kids and programmers (who seem to have forgotten what computers actually are) that its quite fun to mess with programs. We used to have that excitement few years ago, just break into softice and change a branch into a nop and ignore the serial number check, or go to a different game level because this one is too annoying. While working on the game…
2023 · punkx.org · its alternatives →
16
MyraOS – My 32-bit operating system in C and ASM (Hack Club project)▲247
Hi HN, I’m Dvir, a young developer. Last year, I got rejected after a job interview because I lacked some CPU knowledge. After that, I decided to deepen my understanding in the low level world and learn how things work under the hood. I decided to try and create an OS in C and ASM as a way to broaden my knowledge in this area. This took me on the most interesting ride, where I’ve learned about OS theory and low level programming on a whole new level. I’ve spent hours upon hours, blood and tears, reading different OS theory blogs, learning low level concepts, debugging, testing and working on…
Oct 2025 · github.com · its alternatives →
17
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
18
A DOS-like hobby OS written in Rust and x86 assembly▲207
To try it out, simply build the project yourself from source, or use attached bootable ISO image of the system (in Releases on Github) and run it in QEMU. https://blog.vxn.dev/rou2exos-rusted-edition
2025 · github.com · its alternatives →
19
Confidential computing for high-assurance RISC-V embedded systems▲103
Dear HN community! Looking forward to hearing your feedback on ACE (assured confidential execution), technology that implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware. We target high-assurance systems that can benefit from compartmentalization and hardware-backed isolation. The key ingredient called security monitor (firmware) is implemented in Rust. The formal specification is defined as annotations directly in code and gets translated to Coq using RefinedRust automation. ACE design is now part of the…
2025 · github.com · its alternatives →
20
RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint▲7
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
Mar 2026 · github.com · its alternatives →
21
I wrote an OS in 1000 lines of Zig▲151
A minimal RISC-V 32-bit OS written in Zig. Contribute to botirkhaltaev/pico-os development by creating an account on GitHub.
2025 · github.com · its alternatives →
22
I integrated my from-scratch TCP/IP stack into the xv6-riscv OS▲147
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
23
Electrino, a featherweight API-compatible alternative to Electron▲99
Desktop runtime for apps built on web technologies, using the system's own web browser engine - pojala/electrino
2017 · github.com · its alternatives →
24
H2 Forth CPU▲120
A Forth CPU and System on a Chip, based on the J1, written in VHDL - howerj/forth-cpu
2019 · github.com · its alternatives →

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