Porting xv6 to HiFive Unmatched board
Hi HN, I ported the teaching OS xv6-riscv to HiFive Unmatched and got it running on real hardware, including passing usertests. I've been self-studying OS internals using the MIT 6.1810 materials. After finishing most of the labs, I was eager to see what it's like to run the OS on bare metal, rather than QEMU. The Unmatched may not have the latest RISC-V features, but it's well-documented, and the Rev B release has made it more affordable, which makes it a good learning platform. The porting process involved several interesting challenges: - Hardware Quirks: Handling things like enabling…
In plain words
This project demonstrates a successful port of xv6-riscv, an educational operating system, to the HiFive Unmatched RISC-V board, running on actual hardware rather than emulation. Created by a self-taught OS developer working through MIT 6.1810 coursework, the port addresses real hardware challenges including interrupt handling, memory management quirks, and boot flow compatibility. It is for students and hobbyists learning operating system internals who want to run teaching OS code on actual RISC-V hardware. The work stands out for bridging the gap between theoretical OS concepts and practical bare-metal implementation.
written from the facts on this page · September 2026
From the sources
In the maker’s words, at launch
Hi HN, I ported the teaching OS xv6-riscv to HiFive Unmatched and got it running on real hardware, including passing usertests. I've been self-studying OS internals using the MIT 6.1810 materials. After finishing most of the labs, I was eager to see what it's like to run the OS on bare metal, rather than QEMU. The Unmatched may not have the latest RISC-V features, but it's well-documented, and the Rev B release has made it more affordable, which makes it a good learning platform. The porting process involved several interesting challenges: - Hardware Quirks: Handling things like enabling A/D bits in PTEs (the hardware doesn't set them automatically, causing page faults), proper handling of interrupts, and instruction cache synchronization. - Boot Flow: xv6 expects M-mode on startup, but standard RISC-V boot flows (typically via OpenSBI) jump to S-mode. To bridge this gap, I created a minimal U-Boot FIT image that contains only the xv6 kernel. This way, U-Boot SPL handles the complex CPU/DDR initialization, then hands control to xv6 in M-mode (skipping OpenSBI). - Drivers: Ported an SPI SD card driver, replacing the virtio disk driver. I wrote up implementation notes here: https://github.com/eyengin/xv6-riscv-unmatched/blob/unmatche... Hopefully, this is useful for others who are learning OS internals and want to try running their code on real RISC-V hardware.
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