A Project Oberon System version running on RISC-V instead of RISC-5
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
In plain words
This is a modified Project Oberon System that runs on RISC-V (RV32) architecture instead of the original RISC-5. The system has been migrated from Oberon 07 to Oberon 90 and uses the OP2 compiler with a RISC-V backend. It includes a virtual machine emulator that replicates Wirth's original Project Oberon machine design, allowing developers to run Oberon code on RISC-V platforms. The repository contains both the system and emulation tools for developers working with Oberon programming.
written from the facts on this page · September 2026
From the sources
This is a version of the Project Oberon System migrated from Oberon 07 to the more common Oberon 90, using a recent version of the OP2 compiler with a RISC-V (RV32) backend; the repository also includes an emulation of a machine (VM) very similar to the one described by Wirth in his Project Oberon Book , based on the well-known RV32 emulator ; the latter is a stripped-down and slightly modified version with only the interpreter, combined with my own implementation of the machine and the peripherals; the memory map of Wirth's machine is reproduced 1:1 so that Kernel.Mod, Display.Mod and Input.Mod are unchanged. As you might know, between 1986 and 1989, Niklaus Wirth and Jürg Gutknecht at ETH…from github.com
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