RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint launched on March 6, 2026 with 7 votes, #1,458 of 23,380 launches that month and more than 75% of that year's launches.
What it does
A 16-bit 2-cycle RISC-V-inspired CPU in the same footprint as a 65c02. For the SKY130 process Tiny Tapeout. - mysterymath/riscyv02-sky
A 16-bit RISC processor, logically pin-compatible with the WDC 65C02. Designed for Tiny Tapeout SKY130. RISCY-V02 exists to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. cd test && make Hardening cd test && make harden cd test && make metrics Resources Tiny Tapeout LibreLane (hardening flow) TT community Discord About A 16-bit 2-cycle RISC-V-inspired CPU in the same footprint as…from github.com
In the maker’s words, at launch
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design…
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