RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
What it does
In the maker’s words, at launch
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit instructions 2-cycle interrupt entry (vs 7 on 6502) 13,844 SRAM-adjusted transistors (vs 13,176 for 6502 on same process) 1.0-2.6x faster than 6502 across common routines GDS viewer: https://mysterymath.github.io/riscyv02-sky Tiny Tapeout Shuttle Entry: https://app.tinytapeout.com/projects/3829
Does the same job
all alternatives →
A Project Oberon System version running on RISC-V instead of RISC-528d ago · github.com · ▲121Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
- APA pipelined RISC-V processor written in VHDL2015 · github.com · ▲65
- DODiscrete6502 – one thing led to anotherJul 2026 · epatel.github.io · ▲15
Disclaimer, I have not yet placed the order. But JLCPCB have so far excepted all files and config so I have 1 more button to press. If anyone see some obvious mistake please send feedback. This project grew out of curiosity. Loved the https://monster6502.com/ project but that is on another level. Here I tried to stay "reasonable" and added a Raspberry Pico 2 W on the back to drive it all. But also, was curious if Claude could pull this off. Guess I will have to place that order to call the cards.
- ANA nibble-oriented CPU in Verilog to build a scientific calculatorMay 2026 · github.com · ▲119
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
- WBWe built an 8-bit CPU as 2nd year EE studentsJun 2026 · github.com · ▲108
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
More work this month
the category →
The app store for voice native apps that lives in your notch
Work · 28d ago · voiceos.com
The New Calendly▲211Handle all of the work before, during, and after meetings
Work · 17d ago · calendly.com
Launched alongside, March 2026
the whole month →
Switch from ChatGPT to Claude with import memory feature
AI · Mar 2026 · claude.com
