A RISC-V core in Racket
A RISC-V core in Racket launched on April 30, 2021 with 122 votes, #285 of 3,754 launches that month and more than 95% of that year's launches. The site was still online in September 2026, 5 years on.
In plain words
This project is a RISC-V processor core implemented in Racket, a Lisp-based programming language. It allows developers to simulate or study RISC-V instruction set architecture using Racket's functional programming environment. The project is designed for anyone interested in computer architecture, processor design, or learning how CPUs work at a fundamental level. It demonstrates an unconventional approach to hardware simulation by leveraging a high-level language rather than traditional hardware description languages.
written from the facts on this page · September 2026
From the sources
Let’s try to simulate a non-trivial circuit in Racket using the techniques proposed in the previous post . Vermicel is a 32-bit RISC processor core that supports most of the base instruction set of the RISC-V specification (RV32I). It was initially designed and implemented in VHDL under the name « Virgule » to serve as an illustration for the digital electronics course that I taught. The VHDL source code is not publicly available yet but you can get an overview of what Vermicel is by using its web-based simulator emulsiV and reading its documentation . I have written two implementations of Vermicel: one uses a finite state machine as a sequencer; the other is organized as a five-stage…from guillaume.baierouge.fr
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