Life & fun · alternatives · 2026
24 alternatives to A RISC-V core in Racket
This project is a RISC-V processor core implemented in Racket, a Lisp-based programming language. It allows developers to simulate or study RISC-V instruction set architecture using Racket's functional programming… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. A RISC-V core in Racket launched in 2021; newer entries below may have overtaken it.
- 1
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
- 2
I made this game to teach my daughter how buffer overflows work. I want her to look at programs as things she can change, and make them do whatever she wants. Building your exploit in memory and jumping to it feels so cool. I hope this game teaches kids and programmers (who seem to have forgotten what computers actually are) that its quite fun to mess with programs. We used to have that excitement few years ago, just break into softice and change a branch into a nop and ignore the serial number check, or go to a different game level because this one is too annoying. While working on the game…
2023 · punkx.org · its alternatives →
- 3
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
- 4
Introduction to UDP: sockets, frames, and data encoding. We build a Rust client for a simple name server that converts domain names into IP addresses.
2020 · lowlvl.org · its alternatives →
- 5
Long-simmering side project that is finally ready to see the light. HAMTs are a cool persistent data structure and implementing one has been a lot of fun. Beyond the code, there is likely some value in the extensive and largely complete implementation docs; basic benchmarks are linked in the README, too. Kind of aiming to be "the libavl for HAMTs". That is obviously a high and aspirational bar but a distinct possibility if it stirs up a little interest and/or contribution. Anyways, it's time for this to go out, collect feedback and maybe even some use outside of toy projects. Let me…
2023 · github.com · its alternatives →
- 6
2025 · defn.io · its alternatives →
- 7GI
Hi all! I'm going into my freshman year, and figured that the best way to prepare for the intro to programming Racket course would be to implement my own garbage-collected, dynamically typed, functional programming language in C ;) Anyways... here's the repo: https://github.com/liam-ilan/crumb I started learning C over the summer, so I still have a whole lot to learn... Any feedback would be greatly appreciated! :D
2023 · its alternatives →
- 8
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
- 9
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
- 10
Hi everyone, I built PyXL — a hardware processor that executes a custom assembly generated from Python programs, without using a traditional interpreter or virtual machine. It compiles Python -> CPython Bytecode -> Instruction set designed for direct hardware execution. I’m sharing an early benchmark: a GPIO test where PyXL achieves a 480ns round-trip toggle — compared to 14-25 micro seconds on a MicroPython Pyboard - even though PyXL runs at a lower clock (100MHz vs. 168MHz). The design is stack-based, fully pipelined, and preserves Python's dynamic typing without static type restrictions.…
2025 · runpyxl.com · its alternatives →
- 11
This is a hobby project of mine that I started a few years ago to learn about programming language implementation. It was created 95% without AI, although a few recent commits include code from Gemini CLI. I started out following Crafting Interpreters, but gradually branched off that until I had almost nothing left in common. Tech stack: Rust, Cranelift (JIT compilation), LALRPOP (parser). Original title: "A small programming language where everything is a value" (edited based on comments)
Jan 2026 · github.com · its alternatives →
- 12RL
- 13LC
I made a simple virtual machine that runs C in the browser.This project is made as an experiment to see if C can be learned easier if the lower level is covered in paralel. Sandbox: https://vasyop.github.io/miniC-hosting Tutorial part 1: https://vasyop.github.io/miniC-hosting/?0 More info: https://github.com/vasyop/miniC-hosting/blob/master/README.md Please support this project: https://github.com/vasyop/miniC-hosting/blob/master/support.md
2019 · its alternatives →
- 14
I built LocalGPT over 4 nights as a Rust reimagining of the OpenClaw assistant pattern (markdown-based persistent memory, autonomous heartbeat tasks, skills system). It compiles to a single ~27MB binary — no Node.js, Docker, or Python required. Key features: - Persistent memory via markdown files (MEMORY, HEARTBEAT, SOUL markdown files) — compatible with OpenClaw's format - Full-text search (SQLite FTS5) + semantic search (local embeddings, no API key needed) - Autonomous heartbeat runner that checks tasks on a configurable interval - CLI + web interface + desktop GUI - Multi-provider:…
Feb 2026 · github.com · its alternatives →
- 15
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
- 16
Lisp Shell▲120A fully-featured lisp/scheme shell written in Racket. - DexterLagan/lsh
2018 · github.com · its alternatives →
- 17PP
2012 · planet.racket-lang.org · its alternatives →
- 18
Dear HN community! Looking forward to hearing your feedback on ACE (assured confidential execution), technology that implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware. We target high-assurance systems that can benefit from compartmentalization and hardware-backed isolation. The key ingredient called security monitor (firmware) is implemented in Rust. The formal specification is defined as annotations directly in code and gets translated to Coq using RefinedRust automation. ACE design is now part of the…
2025 · github.com · its alternatives →
- 19
Hey HN, I wanted to share the new online playground for Salt (https://salt-lang.dev/playground/), a sovereign systems language designed for high-performance, distributed workloads where paying an "abstraction tax" is no longer acceptable. We started building Salt to bridge the gap between the raw power of manual pointer arithmetic and the safety guarantees of modern high-level languages. The architecture relies on an MLIR-based backbone and a Z3-powered "formal shadow," and the design is rooted in three main pillars: Fast Enough: The target is to stay within 20% of C's…
Jul 2026 · salt-lang.dev · its alternatives →
- 20
Hashed Lookup Table based Matrix Multiplication (halutmatmul) - Stella Nera accelerator - joennlae/halutmatmul
2023 · github.com · its alternatives →
- 21
A minimal stack-based VM. Contribute to codr7/liblg development by creating an account on GitHub.
2020 · github.com · its alternatives →
- 22
A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
2020 · github.com · its alternatives →
- 23
Just released EGG, an emulator created for teaching Assembly and microprocessors (designed to suit the needs of the Microprocessors classes, at Universidade Federal do Paraná, Brazil). The emulator will support multiple architetures in the future, but currently only RISC-V is implemented.
2024 · github.com · its alternatives →
- 24
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
Aug 2026 · github.com · its alternatives →
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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →