Dev tools · alternatives · 2026

24 alternatives to RISC-V core written in 600 lines of C89

32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.

This is a minimal RISC-V processor core implemented in just 600 lines of C89 code. It's designed for developers and hobbyists interested in understanding how processor architecture works or experimenting with RISC-V… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. RISC-V core written in 600 lines of C89 launched in 2023; newer entries below may have overtaken it.

1AR
A RISC-V core in Racket▲122
2021 · guillaume.baierouge.fr · its alternatives →
2
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
3
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
4
RISC-V disassembler in 200 lines of C▲29
A minimal RISC-V RV32I disassembler. Contribute to andportnoy/riscv-disassembler development by creating an account on GitHub.
2020 · github.com · its alternatives →
5
I wrote an OS in 1000 lines of Zig▲151
A minimal RISC-V 32-bit OS written in Zig. Contribute to botirkhaltaev/pico-os development by creating an account on GitHub.
2025 · github.com · its alternatives →
6
IDE for Learning RISC-V▲105
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
7
C++17 RISC-V RV32GC / RV64GC userspace emulator library▲31
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2020 · github.com · its alternatives →
8
RISC-V assembly tabletop board game (hack your opponent)▲400
I made this game to teach my daughter how buffer overflows work. I want her to look at programs as things she can change, and make them do whatever she wants. Building your exploit in memory and jumping to it feels so cool. I hope this game teaches kids and programmers (who seem to have forgotten what computers actually are) that its quite fun to mess with programs. We used to have that excitement few years ago, just break into softice and change a branch into a nop and ignore the serial number check, or go to a different game level because this one is too annoying. While working on the game…
2023 · punkx.org · its alternatives →
9
I integrated my from-scratch TCP/IP stack into the xv6-riscv OS▲147
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
10
A Project Oberon System version running on RISC-V instead of RISC-5▲121
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
Aug 2026 · github.com · its alternatives →
11
Bit Serial CPU▲99
A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial
2020 · github.com · its alternatives →
12
MyraOS – My 32-bit operating system in C and ASM (Hack Club project)▲247
Hi HN, I’m Dvir, a young developer. Last year, I got rejected after a job interview because I lacked some CPU knowledge. After that, I decided to deepen my understanding in the low level world and learn how things work under the hood. I decided to try and create an OS in C and ASM as a way to broaden my knowledge in this area. This took me on the most interesting ride, where I’ve learned about OS theory and low level programming on a whole new level. I’ve spent hours upon hours, blood and tears, reading different OS theory blogs, learning low level concepts, debugging, testing and working on…
Oct 2025 · github.com · its alternatives →
13
CPU simulator in 60 lines of code▲60
Simple CPU model written in 60 lines of C with 8 registers and basic instructions - wkoszek/cpu60
2015 · github.com · its alternatives →
14
A compiler and VM for a simple language, in 150 lines of code▲200
A complete compiler for a simple language (in less than 150 LoC) - 00_readme.md
2022 · gist.github.com · its alternatives →
15H1
Homebrew 16bit CPU from 74HC logic with C compiler and Unix-like OS▲192
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
2023 · sol-1.org · its alternatives →
16
Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V▲115
I pretty much always have a kernel project going on, and have been that way for decades. Over the past couple of years, that's been Anos, which has gotten further along than any of my previous hobby kernels, supporting IPC, multitasking, SMP (x86-64 only right now) and running on real hardware. LLMs (mostly Claude Code) have been used during development, but I learned early on that it's not _great_ at code at this level, so I've restricted its use to mostly documentation and tests. There's _a little_ AI code in the user space, but I have a strict "no AI code" rule in the kernel itself. I…
Apr 2026 · github.com · its alternatives →
17
New RISC-V emulator for Computer Science education▲71
Just released EGG, an emulator created for teaching Assembly and microprocessors (designed to suit the needs of the Microprocessors classes, at Universidade Federal do Paraná, Brazil). The emulator will support multiple architetures in the future, but currently only RISC-V is implemented.
2024 · github.com · its alternatives →
18
A minimal C runtime for Linux i386 and x86_64 in 87 SLOC of C▲172
A minimal C runtime for Linux i386 & x86_64. Contribute to lpsantil/rt0 development by creating an account on GitHub.
2015 · github.com · its alternatives →
19
Confidential computing for high-assurance RISC-V embedded systems▲103
Dear HN community! Looking forward to hearing your feedback on ACE (assured confidential execution), technology that implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware. We target high-assurance systems that can benefit from compartmentalization and hardware-backed isolation. The key ingredient called security monitor (firmware) is implemented in Rust. The formal specification is defined as annotations directly in code and gets translated to Coq using RefinedRust automation. ACE design is now part of the…
2025 · github.com · its alternatives →
20
8-bit CPU simulator in C▲67
A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
2020 · github.com · its alternatives →
21
Emacs-riscv – A RISC-V emulator written in Emacs Lisp▲10
Hi HN, This is a small RISC-V emulator I’ve been hacking on in Emacs Lisp as a fun weekend project. It started mostly as a way to better understand the RISC-V spec by implementing things myself, and also as an excuse to write more non-trivial Emacs Lisp. It currently focuses on RV32I and related basics, and is very much not optimized or production-ready. If you’re into RISC-V, emulators, or just enjoy seeing unusual things built in Emacs Lisp, feedback and comments are welcome Happy hacking!
Jan 2026 · github.com · its alternatives →
22
Libriscv – RISC-V userspace emulator library▲40
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
23
RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint▲7
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
Mar 2026 · github.com · its alternatives →
24
A work-in-progress C compiler from scratch▲159
Programming language that compiles into a x86 ELF executable. - riicchhaarrd/ocean
2021 · github.com · its alternatives →

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