Work · alternatives · 2026
24 alternatives to Emacs-riscv – A RISC-V emulator written in Emacs Lisp
Hi HN, This is a small RISC-V emulator I’ve been hacking on in Emacs Lisp as a fun weekend project. It started mostly as a way to better understand the RISC-V spec by implementing things myself, and also as an excuse to write more non-trivial Emacs Lisp. It currently focuses on RV32I and related basics, and is very much not optimized or production-ready. If you’re into RISC-V, emulators, or just enjoy seeing unusual things built in Emacs Lisp, feedback and comments are welcome Happy hacking!
Emacs-riscv is a RISC-V emulator written in Emacs Lisp that implements the RV32I instruction set and related basics. Created as a weekend project, it serves developers interested in understanding the RISC-V… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes.
- 1
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
- 2
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
- 3
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2020 · github.com · its alternatives →
- 4
I made this game to teach my daughter how buffer overflows work. I want her to look at programs as things she can change, and make them do whatever she wants. Building your exploit in memory and jumping to it feels so cool. I hope this game teaches kids and programmers (who seem to have forgotten what computers actually are) that its quite fun to mess with programs. We used to have that excitement few years ago, just break into softice and change a branch into a nop and ignore the serial number check, or go to a different game level because this one is too annoying. While working on the game…
2023 · punkx.org · its alternatives →
- 5
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
- 6AR
2021 · guillaume.baierouge.fr · its alternatives →
- 7
Demo: https://www.youtube.com/watch?v=f5uygzEmdLw Hi HN, I built a RISC-V emulator that implements the RV32IM instruction set and a minimal syscall interface to run DOOM. A few weeks ago, I got my first output with a simple hello world assembly program. Since then I have been working tirelessly to get DOOM to run. I needed to figure out how to run C programs first, and came across newlib, which allows the underlying environment to implement the syscall stubs one by one until the programs run. I have also added ELF loading, but currently only a single `PT_LOAD` segment is…
May 2026 · github.com · its alternatives →
- 8
Just released EGG, an emulator created for teaching Assembly and microprocessors (designed to suit the needs of the Microprocessors classes, at Universidade Federal do Paraná, Brazil). The emulator will support multiple architetures in the future, but currently only RISC-V is implemented.
2024 · github.com · its alternatives →
- 9
Port of Google v8 engine to RISC-V. Contribute to riscv-collab/v8 development by creating an account on GitHub.
2021 · github.com · its alternatives →
- 10CC
2014 · tuhdo.github.io · its alternatives →
- 11
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
- 12
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
Aug 2026 · github.com · its alternatives →
- 13
A NES Emulator written in Emacs Lisp. Contribute to gongo/emacs-nes development by creating an account on GitHub.
2019 · github.com · its alternatives →
- 14IW
The book page links to a blog post that explains how I got about it (and has a link to sample content), but the TL&DR is that I could not find a lot of books that were on "our" history _and_ were larded with technical details. So I set about writing one, and some five years later I'm happy to share the result. I think it's one of the few "computer history" books that has tons of code, but correct me if I'm wrong (I wrote this both to tell a story and to learn :-)). My favorite languages are Smalltalk and Lisp, but as an Emacs user, I've been using the latter for much longer and for my…
Feb 2026 · berksoft.ca · its alternatives →
- 15
A minimal RISC-V 32-bit OS written in Zig. Contribute to botirkhaltaev/pico-os development by creating an account on GitHub.
2025 · github.com · its alternatives →
- 16
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
- 17
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
- 18
A minimal RISC-V RV32I disassembler. Contribute to andportnoy/riscv-disassembler development by creating an account on GitHub.
2020 · github.com · its alternatives →
- 19
A complete Risc-v RV32I emulator in Rust. Contribute to jawline/risc-v-emulator development by creating an account on GitHub.
2024 · github.com · its alternatives →
- 20
A tiny DIY kit to set up vanilla Emacs for Common Lisp programming - susam/emacs4cl
2020 · github.com · its alternatives →
- 21EC
2022 · emacs.amodernist.com · its alternatives →
- 22
Hi HN, I’m Dvir, a young developer. Last year, I got rejected after a job interview because I lacked some CPU knowledge. After that, I decided to deepen my understanding in the low level world and learn how things work under the hood. I decided to try and create an OS in C and ASM as a way to broaden my knowledge in this area. This took me on the most interesting ride, where I’ve learned about OS theory and low level programming on a whole new level. I’ve spent hours upon hours, blood and tears, reading different OS theory blogs, learning low level concepts, debugging, testing and working on…
Oct 2025 · github.com · its alternatives →
- 23
NTSC-RS▲166Open-source video emulation of analog TV and VHS artifacts
Jun 2026 · ntsc.rs · its alternatives →
- 24
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →