Dev tools · alternatives · 2026
24 alternatives to A straightforward RISC-V 32-bit emulator
A complete Risc-v RV32I emulator in Rust. Contribute to jawline/risc-v-emulator development by creating an account on GitHub.
Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. A straightforward RISC-V 32-bit emulator launched in 2024; newer entries below may have overtaken it.
- 1
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
- 2
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2020 · github.com · its alternatives →
- 3
To try it out, simply build the project yourself from source, or use attached bootable ISO image of the system (in Releases on Github) and run it in QEMU. https://blog.vxn.dev/rou2exos-rusted-edition
2025 · github.com · its alternatives →
- 4
Demo: https://www.youtube.com/watch?v=f5uygzEmdLw Hi HN, I built a RISC-V emulator that implements the RV32IM instruction set and a minimal syscall interface to run DOOM. A few weeks ago, I got my first output with a simple hello world assembly program. Since then I have been working tirelessly to get DOOM to run. I needed to figure out how to run C programs first, and came across newlib, which allows the underlying environment to implement the syscall stubs one by one until the programs run. I have also added ELF loading, but currently only a single `PT_LOAD` segment is…
May 2026 · github.com · its alternatives →
- 5
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
- 6AA
2015 · realscout.github.io · its alternatives →
- 7
NES emulator written in Rust. Contribute to pcwalton/sprocketnes development by creating an account on GitHub.
2013 · github.com · its alternatives →
- 8
Open-source ESP32 emulator. Run real firmware locally or in your browser — no hardware, no cloud, no subscription. - mikroverk/esp32sim
6d ago · github.com · its alternatives →
- 9
Hi HN, This is a small RISC-V emulator I’ve been hacking on in Emacs Lisp as a fun weekend project. It started mostly as a way to better understand the RISC-V spec by implementing things myself, and also as an excuse to write more non-trivial Emacs Lisp. It currently focuses on RV32I and related basics, and is very much not optimized or production-ready. If you’re into RISC-V, emulators, or just enjoy seeing unusual things built in Emacs Lisp, feedback and comments are welcome Happy hacking!
Jan 2026 · github.com · its alternatives →
- 10
A minimal RISC-V 32-bit OS written in Zig. Contribute to botirkhaltaev/pico-os development by creating an account on GitHub.
2025 · github.com · its alternatives →
- 11
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
Aug 2026 · github.com · its alternatives →
- 12
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
- 13
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
- 14AR
2021 · guillaume.baierouge.fr · its alternatives →
- 15
VM with JIT-compiler for ATMega32 written in Rust. Contribute to MackieLoeffel/avr-vm development by creating an account on GitHub.
2017 · github.com · its alternatives →
- 16
Hi HN, I’m Dvir, a young developer. Last year, I got rejected after a job interview because I lacked some CPU knowledge. After that, I decided to deepen my understanding in the low level world and learn how things work under the hood. I decided to try and create an OS in C and ASM as a way to broaden my knowledge in this area. This took me on the most interesting ride, where I’ve learned about OS theory and low level programming on a whole new level. I’ve spent hours upon hours, blood and tears, reading different OS theory blogs, learning low level concepts, debugging, testing and working on…
Oct 2025 · github.com · its alternatives →
- 17RA
2016 · jamesmunns.com · its alternatives →
- 18
Port of Google v8 engine to RISC-V. Contribute to riscv-collab/v8 development by creating an account on GitHub.
2021 · github.com · its alternatives →
- 19
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
- 20
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
- 21
Dear HN community! Looking forward to hearing your feedback on ACE (assured confidential execution), technology that implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware. We target high-assurance systems that can benefit from compartmentalization and hardware-backed isolation. The key ingredient called security monitor (firmware) is implemented in Rust. The formal specification is defined as annotations directly in code and gets translated to Coq using RefinedRust automation. ACE design is now part of the…
2025 · github.com · its alternatives →
- 22
Just released EGG, an emulator created for teaching Assembly and microprocessors (designed to suit the needs of the Microprocessors classes, at Universidade Federal do Paraná, Brazil). The emulator will support multiple architetures in the future, but currently only RISC-V is implemented.
2024 · github.com · its alternatives →
- 23
A minimal RISC-V RV32I disassembler. Contribute to andportnoy/riscv-disassembler development by creating an account on GitHub.
2020 · github.com · its alternatives →
- 24
"Game" is a stretch, but I put together this repo containing a pure Rust app which uses SDL2 and compiles to WASM (and can be run in a browser). Older resources were a bit out of date and a bit too verbose for my purposes, so here's a minimal working example.
2024 · github.com · its alternatives →
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- RISC-V core written in 600 lines of C89 alternatives
- C++17 RISC-V RV32GC / RV64GC userspace emulator library alternatives
- A DOS-like hobby OS written in Rust and x86 assembly alternatives
- I built a RISC-V emulator that runs DOOM alternatives
- Libriscv – RISC-V userspace emulator library alternatives
- Atmel AVR 8-bit Emulator in Rust and React alternatives
Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →