Dev tools · alternatives · 2026

128 userspace emulator library

The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.

Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. C++17 RISC-V RV32/64/128 userspace emulator library launched in 2022; newer entries below may have overtaken it.

1
C++17 RISC-V RV32GC / RV64GC userspace emulator library▲31
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2020 · github.com · its alternatives →
2
Libriscv – RISC-V userspace emulator library▲40
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2022 · github.com · its alternatives →
3
RISC-V core written in 600 lines of C89▲190
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
4
A Fast, Malloc-Free C++14 Json Parser and Encoder▲98
Meta programming utilities for C++14. Merged in matt-42/lithium - matt-42/iod
2014 · github.com · its alternatives →
5
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
6
Compile-time HTML parsing in C++14▲175
A C++ HTML template engine that uses compile time HTML parsing - rep-movsd/see-phit
2017 · github.com · its alternatives →
7
I built a RISC-V emulator that runs DOOM▲50
Demo: https://www.youtube.com/watch?v=f5uygzEmdLw Hi HN, I built a RISC-V emulator that implements the RV32IM instruction set and a minimal syscall interface to run DOOM. A few weeks ago, I got my first output with a simple hello world assembly program. Since then I have been working tirelessly to get DOOM to run. I needed to figure out how to run C programs first, and came across newlib, which allows the underlying environment to implement the syscall stubs one by one until the programs run. I have also added ELF loading, but currently only a single `PT_LOAD` segment is…
May 2026 · github.com · its alternatives →
8
A Project Oberon System version running on RISC-V instead of RISC-5▲121
Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
Aug 2026 · github.com · its alternatives →
9
Look Ma, No Linux: Shell, App Installer, Vi, Cc on ESP32-S3 / BreezyBox▲327
Example repo: https://github.com/valdanylchuk/breezydemo The underlying ESP-IDF component: https://github.com/valdanylchuk/breezybox It is something like Raspberry Pi, but without the overhead of a full server-grade OS. It captures a lot of the old school DOS era coding experience. I created a custom fast text mode driver, plan to add VGA-like graphics next. ANSI text demos run smooth, as you can see in the demo video featured in the Readme. App installs also work smoothly. The first time it installed 6 apps from my git repo with one command, felt…
Feb 2026 · github.com · its alternatives →
10
v8-riscv — Port of JavaScript V8 engine to RISC-V▲123
Port of Google v8 engine to RISC-V. Contribute to riscv-collab/v8 development by creating an account on GitHub.
2021 · github.com · its alternatives →
11
IDE for Learning RISC-V▲105
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
12
Emacs-riscv – A RISC-V emulator written in Emacs Lisp▲10
Hi HN, This is a small RISC-V emulator I’ve been hacking on in Emacs Lisp as a fun weekend project. It started mostly as a way to better understand the RISC-V spec by implementing things myself, and also as an excuse to write more non-trivial Emacs Lisp. It currently focuses on RV32I and related basics, and is very much not optimized or production-ready. If you’re into RISC-V, emulators, or just enjoy seeing unusual things built in Emacs Lisp, feedback and comments are welcome Happy hacking!
Jan 2026 · github.com · its alternatives →
13
A straightforward RISC-V 32-bit emulator▲5
A complete Risc-v RV32I emulator in Rust. Contribute to jawline/risc-v-emulator development by creating an account on GitHub.
2024 · github.com · its alternatives →
14
RISC-V disassembler in 200 lines of C▲29
A minimal RISC-V RV32I disassembler. Contribute to andportnoy/riscv-disassembler development by creating an account on GitHub.
2020 · github.com · its alternatives →
15
OpenVSCode Server▲143
VS Code in the browser for everyone
2021 · github.com · its alternatives →
16
I integrated my from-scratch TCP/IP stack into the xv6-riscv OS▲147
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
17
Rust Vector and Quaternion Lib▲128
I use this library I made for Vectors and Quaternions in many personal projects. I've open-sourced it, in case anyone else would get use out of it. I use this on various projects, including quadcopter firmware, a graphics engine, a cosmology simulation, and several molecular dynamics applications. No_std compatible.
2025 · github.com · its alternatives →
18
Ephemeral VMs in 1 Microsecond▲84
Contribute to libriscv/drogon-sandbox development by creating an account on GitHub.
2024 · github.com · its alternatives →
19
StringZilla v3 with C++, Rust, and Swift bindings, and AVX-512 and NEON▲15
Hi HN! I've spent the last few weeks optimizing the string operations in StringZilla. You'd be surprised how much performance GLibc and the Standard Templates Library of C++ are leaving on the table, especially on Arm and, likely, on RISC-V. I've significantly increased the number of implemented algorithms for different workloads. Searching across English texts on Arm, for example: - is 4.4x faster than STL, - and 16.8x faster in reverse order. The new version of the library now includes a C++ binding largely compatible with the C++ Standard, featuring all 17 overloads of the `replace`…
2024 · github.com · its alternatives →
20
Pbnj – A minimal, self-hosted pastebin you can deploy in 60 seconds▲69
I'm sure folks here have seen pastebins a thousand times. There's no innovation left in this space – and that's kind of the point. When I wanted to self-host a pastebin, every option I found was too much. Git-based version control, OAuth, elaborate admin panels. I just wanted something I could deploy in under a minute with a CLI that actually works. So I built pbnj (yes, like the sandwich). What it is: - A minimal, beautiful pastebin with syntax highlighting for 100+ languages - One-click deploy to Cloudflare (free tier gives you ~100,000 pastes) - CLI-first: pbnj file.py → get a URL, copied…
Dec 2025 · pbnj.sh · its alternatives →
21
AVR-VM – VM with JIT-compiler for ATMega32 written in Rust▲78
VM with JIT-compiler for ATMega32 written in Rust. Contribute to MackieLoeffel/avr-vm development by creating an account on GitHub.
2017 · github.com · its alternatives →
22
Fast Random Library for C++17▲52
Morning HN. Random number generation feels is a somewhat underrepresented topic in the C++ realm. There is a lot of questionable info about it found online and even the standard library is quite behind the times in terms of it's algorithms. It suffers from trying to accommodate sometimes impractical standard requirements and has several ways of getting significantly bad statistical results. This leaves a lot easily achievable performance & quality on the table. So, being a mathematician who mostly works with stochastic models and wants these models to run fast and well, I embarked on a…
2025 · github.com · its alternatives →
23
Beating GCC 12 – 118x Speedup for Jensen Shannon D. Via AVX-512FP16▲8
SIMD-accelerated distances, dot products, matrix ops, geospatial & geometric kernels for 16 numeric types — from 6-bit floats to 64-bit complex — across x86, Arm, RISC-V, and WASM, with bindings for Python, Rust, C, C++, Swift, JS, and Go 📐 - Release Beating GCC 12 - 118x Speedup for Jensen Shannon
2023 · github.com · its alternatives →
24
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →

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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →