C++17 RISC-V RV32/64/128 userspace emulator library
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
C++17 RISC-V RV32/64/128 userspace emulator library launched on November 20, 2022 with 5 votes, #1,507 of 3,471 launches that month and more than 50% of that year's launches. The site was still online in September 2026, 3 years on.
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C++17 RISC-V RV32GC / RV64GC userspace emulator library2020 · github.com · ▲31The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
Libriscv – RISC-V userspace emulator library2022 · github.com · ▲40The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
RISC-V core written in 600 lines of C892023 · github.com · ▲19032-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
A Fast, Malloc-Free C++14 Json Parser and Encoder2014 · github.com · ▲98Meta programming utilities for C++14. Merged in matt-42/lithium - matt-42/iod
Minimax – A Compressed-First, Microcoded RISC-V CPU2022 · github.com · ▲171RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
Compile-time HTML parsing in C++142017 · github.com · ▲175A C++ HTML template engine that uses compile time HTML parsing - rep-movsd/see-phit
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