Life & fun · alternatives · 2026

24 alternatives to Write, simulate and synthesize VHDL/Verilog in the browser

Learn digital hardware design in the browser: write VHDL and SystemVerilog, simulate, read waveforms, and synthesize to a netlist. No installation required.

This is a browser-based tool for writing, simulating, and synthesizing VHDL and Verilog code. It allows hardware engineers and students to develop digital designs directly in a web interface without installing… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes.

1
Verilog2factorio▲313
This project will compile verilog (a hardware description language) into factorio blueprints. - Redcrafter/verilog2factorio
2021 · github.com · its alternatives →
2
I made a little digital circuit simulator that operates on PNGs▲259
This is a little toy project of mine that lets you simulate digital logic graphs. It was inspired by Minecraft's Redstone and the Piet esolang. It's got some serious drawbacks-- you write circuits as PNGs and simulate them with a Python interface. It's slow to run and slow to experiment with. And it is certainly difficult to use for people with any kind of color blindness. But despite that, I hope this can still be a fun toy!
2022 · github.com · its alternatives →
3
v0.dev by Vercel▲549
Generate UI with simple text prompts: copy, paste, ship
2023 · v0.app · its alternatives →
4
Scratchboard▲146
Create, simulate, and collaborate on digital circuits
2025 · scratchboard.io · its alternatives →
5VP
VHDL pseudo random generator tutorial (three parts)▲14
2016 · fpgasite.net · its alternatives →
6
Modo▲148
I’ve built hardware projects for years, and the gap between “I want X” and “parts ordered, files ready to print” always took weeks. Modo compresses that. Describe what you want (e.g. “a portable CO2 monitor with a display and buzzer”) and it generates: - A bill of materials with real components (MPNs, not hallucinated parts) - A printable enclosure generated from actual part dimensions - Wiring diagrams, firmware boilerplate, and assembly instructions - Design validation (power budget, pin conflicts, mechanical fit) Everything streams in real time as each phase completes. The key idea is…
Jan 2026 · modo.is · its alternatives →
7
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
8
Bit Serial CPU▲99
A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial
2020 · github.com · its alternatives →
9
Vulkos▲3
Semiconductor design just got easy
Jul 2026 · vulkos.co.uk · its alternatives →
10
Open-source, configurable HDMI output for FPGAs▲195
Send video/audio over HDMI on an FPGA. Contribute to hdl-util/hdmi development by creating an account on GitHub.
2020 · github.com · its alternatives →
11
8-bit CPU simulator in C▲67
A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
2020 · github.com · its alternatives →
12MA
Manta – A tool for FPGA Debugging and Rapid Prototyping▲86
Hi HN! I'm Fischer, and I'm super stoked to share a project that I've been working on for a little over a year: Manta, an open-source, cross-platform, vendor-independent tool for debugging and rapid prototyping with FPGAs. This was originally my Master's Thesis at MIT, where I developed it for our course on FPGA design. We needed an alternative to vendor debugging tools, which only supported x86 machines running Windows or Linux. We were able to patch in macOS support with VMs, but as more students came bringing ARM-based devices, we needed a new tool. So I developed this. It's called Manta,…
2024 · fischermoseley.github.io · its alternatives →
13
I made a digital circuit drawing and simulation game▲139
Inspired by games like Turing Complete/Virtual Circuit Board/Logic World, I tried to make a mix of aseprite and wiredworld/wired-logic, the idea being the user can build a digital circuit using a "fullstack" pixelart creation workflow. The circuit is just an image. The primitives are (i) connected wires which have undefined, 0 or 1 state during simulation (displayed brighter or darker in function of the state) and (ii) NANDs, which are little pixel triangles. During simulation the user can interact with any wire by clicking on it, toggling its state, which is cool for messing…
2024 · github.com · its alternatives →
14IM
I made some transistor animations▲212
Hi HN, I made some animations of the most important kinds of transistors using my semiconductor simulation, details of which are on the page. I tried to make the visuals as realistic as possible while also aiming for clarity. If you want to go beyond the charge carriers and look at, for example, the electric field, you can do so in the simulation software. The desktop software also has less common devices like IBGTs and SCRs that have similar animations. The last thread about my software was posted here about a year ago: https://news.ycombinator.com/item?id=43942279
Jul 2026 · brandonli.net · its alternatives →
15
A DOS-like hobby OS written in Rust and x86 assembly▲207
To try it out, simply build the project yourself from source, or use attached bootable ISO image of the system (in Releases on Github) and run it in QEMU. https://blog.vxn.dev/rou2exos-rusted-edition
2025 · github.com · its alternatives →
16
A small virtual machine written in C▲212
"interesting" VM in C. Let's see how this goes. Contribute to tekknolagi/carp development by creating an account on GitHub.
2014 · github.com · its alternatives →
17
A nibble-oriented CPU in Verilog to build a scientific calculator▲119
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com · its alternatives →
18
EasyCircuit▲178
Hardware prototyping, as simple as vibe-coding
Jul 2026 · easycircuit.app · its alternatives →
19
SHDL – A minimal hardware description language built from logic gates▲48
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…
Jan 2026 · github.com · its alternatives →
20
VisCircuit – A Note-Taking Website for Electronics and Circuits▲120
Hi, everyone. I created a note-taking website for electronics and circuits where you can draw circuit diagrams and write text notes at the same time. I am a Digital IC designer, and I self-study different types of analog and digital circuits a lot. However, I found a problem. Circuits have many different architectures and are hard to memorize due to numerous experiential tips. I want to document what I learn in my note app, but I found there is no method for me to easily draw circuit and block diagrams alongside text notes. This issue has bothered me for a long time, from my master's school…
2024 · viscircuit.com · its alternatives →
21
What if your synthesizer was powered by APL (or a dumb K clone)?▲92
I built k-synth as an experiment to see if a minimalist, K-inspired array language could make sketching waveforms faster and more intuitive than traditional code. I’ve put together a web-based toolkit so you can try the syntax directly in the browser without having to touch a compiler: Live Toolkit: https://octetta.github.io/k-synth/ If you visit the page, here is a quick path to an audio payoff: - Click "patches" and choose dm-bell.ks. - Click "run"—the notebook area will update. Click the waveform to hear the result. - Click the "->0" button below the waveform to copy…
Mar 2026 · octetta.github.io · its alternatives →
22
A realtime node-based audio synth based on LLVM▲78
A powerful realtime node-based audio synthesizer. Contribute to monadgroup/axiom development by creating an account on GitHub.
2018 · github.com · its alternatives →
23
TypMo▲154
Hello HN! I’ve been working on a small tool that helps you move from quick wireframe experiments to solid, production-ready prompts. As a designer, I’ve always felt that getting the structure right early saves a ton of pain later. TypMo leans into that idea by grounding everything in IA-style wireframes- fast to create, easy to iterate, and perfect for figuring out what you actually mean before throwing prompts at AI. I’m now pushing it a step further with a lightweight DSL. Still early, still rough around the edges, but with some AI help it’s starting to feel real. Would love to hear what…
Dec 2025 · typmo.com · its alternatives →
24
We built an 8-bit CPU as 2nd year EE students▲108
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com · its alternatives →

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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →