nowfound

Life & fun · September 30, 2016

VP

VHDL pseudo random generator tutorial (three parts)

VHDL pseudo random generator tutorial (three parts) launched on September 30, 2016 with 14 votes, #1,645 of 3,743 launches that month and more than 75% of that year's launches.

In plain words

This tutorial in three parts teaches how to build a pseudo random generator in VHDL, a hardware description language used for digital circuit design. It is aimed at engineers and students learning FPGA development. The tutorial covers the practical implementation of random number generation in hardware, breaking down the concept into manageable sections for learners to understand and apply to their own projects.

written from the facts on this page · September 2026

Does a similar job

all alternatives →
  • A tiny and platform-agnostic true random number generator for FPGA/ASIC2023 · github.com · ▲27

    It is based on phase noise, consumes less than 60 LUT4s/FFs and achieves up to 7.99 bits of entropy per byte. Feel free to comment if you have any questions, ideas or thoughts :)

  • Write, simulate and synthesize VHDL/Verilog in the browserJul 2026 · risingedge.pro · ▲19

    Learn digital hardware design in the browser: write VHDL and SystemVerilog, simulate, read waveforms, and synthesize to a netlist. No installation required.

  • Simple way to obtain pseudorandomness from CPU context switch in Go2018 · github.com · ▲34

    Pseudorandom generator written in Go using CPU context switch - maxamel/BitGenGo

  • Fast Random Library for C++172025 · github.com · ▲52

    Morning HN. Random number generation feels is a somewhat underrepresented topic in the C++ realm. There is a lot of questionable info about it found online and even the standard library is quite behind the times in terms of it's algorithms. It suffers from trying to accommodate sometimes impractical standard requirements and has several ways of getting significantly bad statistical results. This leaves a lot easily achievable performance & quality on the table. So, being a mathematician who mostly works with stochastic models and wants these models to run fast and well, I embarked on a…

  • SHDL – A minimal hardware description language built from logic gatesJan 2026 · github.com · ▲48

    Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…

  • A pipelined RISC-V processor written in VHDL2015 · github.com · ▲65

    A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.

More life & fun this month

the category →

Source: Show HN post ↗

Launched alongside, September 2016

the whole month →
  • Real decks from real startups that raised over $400M

    Growth · 2016 · cirrusinsight.com

  • Bitmap & tilemap generation from a single example with the help of ideas from quantum mechanics - mxgmn/WaveFunctionCollapse

    Life & fun · 2016 · github.com

  • Smart messaging app that helps you say more and do more.

    Work · 2016 · android.com

  • Reproducing images with geometric primitives. Contribute to fogleman/primitive development by creating an account on GitHub.

    Dev tools · 2016 · github.com

  • Embedded camera sunglasses by Snapchat

    Work · 2016 · spectacles.com

  • AccessURL▲818

    Share access to accounts without sending a username/password

    Life & fun · 2016 · accessurl.com