A tiny and platform-agnostic true random number generator for FPGA/ASIC
It is based on phase noise, consumes less than 60 LUT4s/FFs and achieves up to 7.99 bits of entropy per byte. Feel free to comment if you have any questions, ideas or thoughts :)
A tiny and platform-agnostic true random number generator for FPGA/ASIC launched on November 4, 2023 with 27 votes, #1,227 of 4,333 launches that month and more than 75% of that year's launches. The site was still online in September 2026, 2 years on.
In plain words
This is a true random number generator designed for FPGAs and ASICs that uses phase noise to produce random bits. It requires minimal hardware resources, consuming fewer than 60 LUT4s and flip-flops, while generating up to 7.99 bits of entropy per byte. The tool is platform-agnostic and targets hardware engineers and developers who need efficient random number generation for cryptographic or simulation purposes on integrated circuits.
written from the facts on this page · September 2026
From the sources
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). - stnolting/neoTRNG
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A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA2021 · github.com · ▲5🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). - stnolting/neoTRNG
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