Life & fun · alternatives · 2026
24 alternatives to VHDL pseudo random generator tutorial (three parts)
This tutorial in three parts teaches how to build a pseudo random generator in VHDL, a hardware description language used for digital circuit design. It is aimed at engineers and students learning FPGA development. The… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. VHDL pseudo random generator tutorial (three parts) launched in 2016; newer entries below may have overtaken it.
- 1
It is based on phase noise, consumes less than 60 LUT4s/FFs and achieves up to 7.99 bits of entropy per byte. Feel free to comment if you have any questions, ideas or thoughts :)
2023 · github.com · its alternatives →
- 2
Learn digital hardware design in the browser: write VHDL and SystemVerilog, simulate, read waveforms, and synthesize to a netlist. No installation required.
Jul 2026 · risingedge.pro · its alternatives →
- 3
Pseudorandom generator written in Go using CPU context switch - maxamel/BitGenGo
2018 · github.com · its alternatives →
- 4
Morning HN. Random number generation feels is a somewhat underrepresented topic in the C++ realm. There is a lot of questionable info about it found online and even the standard library is quite behind the times in terms of it's algorithms. It suffers from trying to accommodate sometimes impractical standard requirements and has several ways of getting significantly bad statistical results. This leaves a lot easily achievable performance & quality on the table. So, being a mathematician who mostly works with stochastic models and wants these models to run fast and well, I embarked on a…
2025 · github.com · its alternatives →
- 5
This is a little toy project of mine that lets you simulate digital logic graphs. It was inspired by Minecraft's Redstone and the Piet esolang. It's got some serious drawbacks-- you write circuits as PNGs and simulate them with a Python interface. It's slow to run and slow to experiment with. And it is certainly difficult to use for people with any kind of color blindness. But despite that, I hope this can still be a fun toy!
2022 · github.com · its alternatives →
- 6
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…
Jan 2026 · github.com · its alternatives →
- 7
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
- 8RA
2022 · joelkp.frama.io · its alternatives →
- 9
:game_die: Generate "truly" random numbers (WARNING: NOT RANDOM!!! The "truly" is in sarcasquotes) - jaybosamiya/true-random
2016 · github.com · its alternatives →
- 10
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). - stnolting/neoTRNG
2021 · github.com · its alternatives →
- 11
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com · its alternatives →
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I built DDL to Data after repeatedly pushing back on "just use production data and mask it" requests. Teams needed populated databases for testing, but pulling prod meant security reviews, PII scrubbing, and DevOps tickets. Hand-written seed scripts were the alternative slow, fragile, and out of sync the moment schemas changed. Paste your CREATE TABLE statements, get realistic test data back. It parses your schema, preserves foreign key relationships, and generates data that looks real, emails look like emails, timestamps are reasonable, uniqueness constraints are honored. No setup, no…
Jan 2026 · ddltodata.com · its alternatives →
- 14
Generating fun Stack Overflow and Stack Exchange Questions using Markov Chains
2018 · se-simulator.lw1.at · its alternatives →
- 15
Inspired by games like Turing Complete/Virtual Circuit Board/Logic World, I tried to make a mix of aseprite and wiredworld/wired-logic, the idea being the user can build a digital circuit using a "fullstack" pixelart creation workflow. The circuit is just an image. The primitives are (i) connected wires which have undefined, 0 or 1 state during simulation (displayed brighter or darker in function of the state) and (ii) NANDs, which are little pixel triangles. During simulation the user can interact with any wire by clicking on it, toggling its state, which is cool for messing…
2024 · github.com · its alternatives →
- 16
Simple and easy to use ad-free number generator
2021 · play.google.com · its alternatives →
- 17BA
I am a Dutch high school student and last year I had to do a large project of my own choice. Together with two other guys I decided to do a project about digital logic. We had an ambitious plan: building an 8-bits computer. At that time I started learning programming and I already knew some HTML and CSS. So we decided to not build a physical computer, but one running in a self-built simulator. I was going to build the simulator, the other guys took care of the computer. I was hard, our school hadn't taught us anything about computers and programming so we had to learn everything ourselves.…
2017 · its alternatives →
- 18SF
2020 · espadrine.github.io · its alternatives →
- 19MA
Hi HN! I'm Fischer, and I'm super stoked to share a project that I've been working on for a little over a year: Manta, an open-source, cross-platform, vendor-independent tool for debugging and rapid prototyping with FPGAs. This was originally my Master's Thesis at MIT, where I developed it for our course on FPGA design. We needed an alternative to vendor debugging tools, which only supported x86 machines running Windows or Linux. We were able to patch in macOS support with VMs, but as more students came bringing ARM-based devices, we needed a new tool. So I developed this. It's called Manta,…
2024 · fischermoseley.github.io · its alternatives →
- 20
A bit-serial CPU written in VHDL, with a simulator written in C. - howerj/bit-serial
2020 · github.com · its alternatives →
- 21
Haskell for FPGA Hardware Design: Use abstractions like monads and lenses to implement 1970
2021 · unsafeperform.io · its alternatives →
- 22
Haskell re-implementation of STOKE, the stochastic superoptimizer - blaze/notebooks/tutorial.ipynb at master · bollu/blaze
2019 · github.com · its alternatives →
- 23
Generate unique random password in few clicks
2021 · goonlinetools.com · its alternatives →
- 24
Also compare
- A tiny and platform-agnostic true random number generator for FPGA/ASIC alternatives
- Write, simulate and synthesize VHDL/Verilog in the browser alternatives
- Simple way to obtain pseudorandomness from CPU context switch in Go alternatives
- Fast Random Library for C++17 alternatives
- I made a little digital circuit simulator that operates on PNGs alternatives
- SHDL – A minimal hardware description language built from logic gates alternatives
Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →