SHDL – A minimal hardware description language built from logic gates
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…
SHDL – A minimal hardware description language built from logic gates launched on January 28, 2026 with 48 votes, #559 of 14,584 launches that month and more than 95% of that year's launches.
In plain words
SHDL is a minimal hardware description language that removes abstractions and requires builders to construct digital circuits explicitly from logic gates and wires. Designed for learning and experimentation rather than production synthesis, it offers no arithmetic operators, implicit bit widths, or high-level constructs. Users compose circuits hierarchically and test them through PySHDL, a Python interface for simulation. The language compiles to C for execution while maintaining transparency and simplicity, making it suitable for engineers and students studying digital logic from foundational principles.
written from the facts on this page · September 2026
From the sources
A minimalist HDL built entirely from logic gates for education and experimentation. Compiles circuits to C so that they can run anywhere - rafa-rrayes/SHDL
SHDL (Simple Hardware Description Language) is an educational, gate-level hardware description language and simulation toolchain. Its founding principle is fidelity : circuits simulate gate by gate, one propagation level per cycle (the unit-delay model), and no tool in the chain is allowed to collapse or shortcut that structure. You describe hardware out of AND/OR/NOT/XOR; you watch signals ripple through it. SHDL is the authoring language: reusable hierarchical components, multi-bit ports, compile-time parameters, generators and conditionals for repetitive structure, bit slices and concatenation, named constants, optional initial state, and imports. Specified in docs/shdl.md . Base SHDL is…from github.com
In the maker’s words, at launch
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then…
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