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Life & fun · March 24, 2023

Naja-Verilog – Structural Verilog Parser

A standalone structural (gate-level) verilog parser - najaeda/naja-verilog

Naja-Verilog – Structural Verilog Parser launched on March 24, 2023 with 17 votes, #1,773 of 5,007 launches that month and more than 75% of that year's launches. The site was still online in September 2026, 3 years on.

Visit github.com ↗Alternatives

In plain words

Naja-Verilog is a structural Verilog parser that reads and processes Verilog hardware description language files. It is designed for developers and engineers who work with digital design and need to parse Verilog code programmatically. The parser focuses on extracting and analyzing the structural components of Verilog designs, making it useful for design verification, analysis, and tool development in the hardware engineering workflow.

written from the facts on this page · September 2026

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