SatCat5, the open-source FPGA Ethernet switch
We've just launched v2.5 of SatCat5, the open-source FPGA Ethernet switch [1]. SatCat5 contains various FPGA building blocks that let you build a custom mixed-media Ethernet switch. It was originally intended for cubesats [2] but has many other potential applications. The headline feature for this release is support for the IEEE-1588 Precision Time Protocol (PTP). SatCat5 has demonstrated end-to-end synchronization to within 50 ps-rms, which is approaching the world-leading performance of CERN's White Rabbit Project [3]. Except we're doing time-transfer over regular, non-synchronous…
In plain words
SatCat5 is an open-source FPGA Ethernet switch composed of configurable building blocks for creating custom mixed-media switches. Originally designed for cubesats, it serves applications requiring custom network solutions. Version 2.5 adds IEEE-1588 Precision Time Protocol support, achieving end-to-end synchronization within 50 picoseconds using standard Ethernet through a novel digital timestamping technology. It is licensed under CERN-OHL-W v2.0 and targets developers and engineers building specialized networking hardware.
written from the facts on this page · September 2026
From the sources
In the maker’s words, at launch
We've just launched v2.5 of SatCat5, the open-source FPGA Ethernet switch [1]. SatCat5 contains various FPGA building blocks that let you build a custom mixed-media Ethernet switch. It was originally intended for cubesats [2] but has many other potential applications. The headline feature for this release is support for the IEEE-1588 Precision Time Protocol (PTP). SatCat5 has demonstrated end-to-end synchronization to within 50 ps-rms, which is approaching the world-leading performance of CERN's White Rabbit Project [3]. Except we're doing time-transfer over regular, non-synchronous Ethernet. The key breakthrough is a new technology for digital timestamps that we've published in IEEE Access [4]. This project was featured on HN back in 2023 [5]. Since then, we've changed to the CERN-OHL-W v2.0 license, which has much better legal clarity for FPGA projects. [1] https://github.com/the-aerospace-corporation/satcat5 [2] https://digitalcommons.usu.edu/smallsat/2020/all2020/174/ [3] https://white-rabbit.web.cern.ch/documents/White_Rabbit-a_PT... [4] https://ieeexplore.ieee.org/abstract/document/10367970 [5] https://news.ycombinator.com/item?id=34817550
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