GitHub
Ai zip compression
GitHub launched on May 4, 2026 with 3 votes, #3,449 of 20,538 launches that month and more than 50% of that year's launches. The site was not reachable when checked in September 2026.
What it does
Adaptive Neural Compression (ANC) -- AI-powered compression at every level: Gestalt prompt shortening, ZIP-RAM communication, Synapse Indexing - danielmigrow-alt/zip-ai
Does a similar job
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Neural Image Compression Demo2020 · colab.research.google.com · ▲78
HiFiC – High-Fidelity Generative Image Compression – demo and paper2020 · hific.github.io · ▲281We combine Generative Adversarial Networks with learned compression to obtain a state-of-the-art generative lossy compression system.
Thinc, a new deep learning library by the makers of spaCy and FastAPI2020 · thinc.ai · ▲250Thinc is a lightweight type-checked deep learning library for composing models, with support for layers defined in frameworks like PyTorch and TensorFlow.

misa77 - a codec that decodes 2x faster than LZ4 (at better ratios)Jul 2026 · github.com · ▲164I've spent the last few months working on this codec. It has the following characteristics: - SOTA decompression throughput in its ratio class - Decent ratios (comparable to LZ4 at high effort levels) - Slow compression Most of the gains can be attributed to reducing branches and making decompression very friendly to out-of-order cores, by using a smart format. Results on the tarred Silesia corpus on Intel x86-64 follow: codec decode ratio encode misa77 -0 5219 MB/s 42.64% 54.5 MB/s misa77 -1 4274 MB/s 39.65% 51.2 MB/s lz4 2505 MB/s 47.59% 371 MB/s lz4hc -12…
Minimax – A Compressed-First, Microcoded RISC-V CPU2022 · github.com · ▲171RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
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