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Life & fun · January 15, 2023

Hlb-CIFAR10 0.2.0: New world record (~<12.38s) on single-GPU CIFAR10

Hello everyone, After recreating the accuracy&#x2F;rough speed from David Page's implementation in hlb-CIFAR10 0.1.0 (18.1s on an A100, SXM4, Colab), it was down to some basic NVIDIA kernel profiling to figure out which operations were the long poles in the tent. Perhaps (somewhat?) unsurprisingly, the NCHW NHWC thrash was the worst part, but unfortunately the GhostBatchNorm was a barrier even using the faster-on-Ampere channels_last memory format. A quick note before continuing -- some may find the use of a convolutional network and on CIFAR10 to be curious. A quick answer to that would be…

Hlb-CIFAR10 0.2.0: New world record (~<12.38s) on single-GPU CIFAR10 launched on January 15, 2023 with 7 votes, #1,589 of 3,901 launches that month and more than 50% of that year's launches. The site was still online in September 2026, 3 years on.

What it does

Train to 94% on CIFAR-10 in <6.3 seconds on a single A100. Or ~95.79% in ~110 seconds (or less!) - Release beta v0.2.0 (~12.31-12.38s) · tysam-code/hlb-CIFAR10

New speed: ~12.31-12.38 seconds on an A100 SXM4 (through Colab). Many, many thanks to @99991 ( https://github.com/99991/cifar10-fast-simple ) for their help with finding the issues that eventually led to some of these improvements, as well as detailed debugging and verification of results on their end. I encourage you to check out some of their work! <3 :) -- Swap the memory channels out for channels_last (in beta for pytorch currently) -- Replace the nn.AdaptiveMaxPooling with a similarly-named class wrapping torch.amax (nearly a ~.5 second speedup in total) -- Replace GhostNorm with a more noisy BatchNorm to take advantage of the faster/simpler kernels. This resulted in roughly a 5.25…from github.com

In the maker’s words, at launch

Hello everyone, After recreating the accuracy&#x2F;rough speed from David Page's implementation in hlb-CIFAR10 0.1.0 (18.1s on an A100, SXM4, Colab), it was down to some basic NVIDIA kernel profiling to figure out which operations were the long poles in the tent. Perhaps (somewhat?) unsurprisingly, the NCHW <-> NHWC…

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