Alternatives
Products that do what Intel PMU Profiling does
See https://github.com/rodgarrison/rdpmc If you've been interested in micro-benchmarking code using Intel's PMU HW capability to capture per HW core metrics, this repository may be for you. The repository includes 'doc/pmu.md' with a copy of Intel's software reference manuals (PDF) so, all in one place, you can understand and develop PMU profiling for your Intel micro architecture. Example included. Source code is 451 LOC with comments. Features: * Minimum, complete * Does not require yum install msr-tools * Header only: include and you're done * Works in user-space…
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- 2SP
2017 · github.com
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- 4CS
2015 · github.com
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- 7PB
2021 · github.com
- 8PS
2015 · github.com
- 98B
2020 · github.com
- 10CA
A recent HackerNews comment - “For one programmer's hourly cost, you could run 4000 CPU cores continuously. Can there really be no practical way to apply thousands of cores to boosting the programmer's productivity?” https://news.ycombinator.com/item?id=19339467 This is what we have come up with. The current productivity tools - Slack, Asana, Trello, Facebook Workplace, etc. - are great, but lack direct access to your code. Building a tool directly around the code makes it more powerful for software developers: CoDiff. https://codiff.com The foundation of CoDiff is a…
2019
- 11PA
2019 · github.com
- 12QH
2015 · github.com
- 13IM
This is a personal project I've been working on and off for the past few years. It's a set of tools that have allowed me to prototype quickly small (and increasingly bigger) kernels, and create userspace programs to interact with them. Supports riscv64, amd64 and i386. The intel port has been tested and used on real hardware, from big dual-socket Xeon machines to an old X220. It is all C, I have plan to make rust bindings for the kernel library. But again, they're plans at this stage. Porting to new architectures is relatively simple, a basic port to riscv took me a couple of weeks of…
2024 · github.com
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I made this after seeing someone posit the idea online yesterday over lunch then spent some time refining it. So far it's pretty impressive IMO! Right now I am running Qwen3-30B-A3B on my 24gb unified memory m4 MacBook Pro at 50 tok/sec and this should definitely not be working for such a large model on my middling hardware. Things are detailed in the README to get up and running and DESIGN.md has details on all the choices and such made along the way.
22d ago · github.com
- 15IM
It's a chrome extension that automatically loads the specs from the Hugging Face model card into the calculation. > To test it, install the extension (no registration/key needed) and navigate to a HF model page. Then click the "VRAM" icon on the top right to open the sidepanel. You can specify quantization, batch size, sequence length, etc. Works for inference & fine-tuning. If it does not fit on the specified GPUs, it gives you an advise on how to still run it (e.g. lowering precision). It is inspired at my work, where we were constantly exporting metrics from HF to estimate required…
2025 · chromewebstore.google.com
- 16RV
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
Mar 2026 · github.com
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Hey HN, Recently built an Apple II emulator and at the same time was getting into Tiny Tapeout and decided it would be cool to build a cycle-accurate 6502 CPU and an MCU for it. It's cycle accurate and the core itself should be 100% compatible with a stock MOS 6502 (would need to still test this though!). Tested on some FPGAs (fomu, ulx3s) and works great, hoping to get it taped out in the upcoming IHP26a shuttle. Also as part of the project I built a bus multiplexer to allow memory/bus access from an RP2040 to work around the limited pin count on Tiny Tapeout. This let's you load up…
Feb 2026 · github.com
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I've worked on several projects writing and implementing specifications (particularly CLN): I've found the specs I write are much better when I quote them in the implementation, so I can see what implementers need to know. Also, when specs change in development, it's almost trivial to find where to update the code. This project is a formalization of my various hacky scripts which ensure the requirements are accurately quoted, and give coverage if any are missing. Not a major Opus, but I hope someone else finds it useful!
Jul 2026 · greatspectations.org
- 19TM
2014 · lowrisc.org
- 20AM
2021 · github.com
- 21IB
Built a simple web app that tells you which open-source LLMs will work on your hardware. It auto-detects your specs, shows compatible models from Hugging Face, gives realistic performance estimates (tokens/sec), and recommends quantization settings. You can also manually input specs to see "what if I upgraded my RAM?" Made this after wasting time downloading giant models only to find they crawled on my hardware. Hope it saves you some frustration!
2025 · caniusellm.com
- 22HC
Hello everyone, After recreating the accuracy/rough speed from David Page's implementation in hlb-CIFAR10 0.1.0 (18.1s on an A100, SXM4, Colab), it was down to some basic NVIDIA kernel profiling to figure out which operations were the long poles in the tent. Perhaps (somewhat?) unsurprisingly, the NCHW NHWC thrash was the worst part, but unfortunately the GhostBatchNorm was a barrier even using the faster-on-Ampere channels_last memory format. A quick note before continuing -- some may find the use of a convolutional network and on CIFAR10 to be curious. A quick answer to that would be…
2023 · github.com
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Hi HN! We’re the team behind CodSpeed (https://codspeed.io), a continuous performance testing tool. Today, we're really excited to launch our new product: p99 (https://p99.chat), an assistant for software performance optimization. Through CodSpeed, we have been working with hundreds of projects doing performance optimization. What struck us was how fragmented the tooling landscape is. You would identify a performance regression in their CI, or worse, in production, then disappear into a rabbit hole of benchmarking frameworks, sampling profilers, memory profilers,…
2025 · p99.chat
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I built a 16-bit CPU simulator that runs entirely in the browser. You can write assembly, run it, or step through it one instruction at a time while watching what happens inside the CPU. It shows the registers, memory, flags, ALU, buses, and datapath as the program executes. You can also set breakpoints, inspect execution cycles, replay previous cycles, and try some example programs. I built this because I wanted CPU architecture to feel more tangible. Reading about fetch, decode, registers, buses, and the ALU is one thing. Watching an instruction actually move through the CPU is much more…
24d ago · coretrace.srianjaneyam.me
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