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Products that do what Running BitNet b1.58 inside DRAM by breaking DDR4 timing rules does
I have been working on running BitNet b1.58 inside DRAM by intentionally breaking DDR4 timing rules. Also made a visual explainer: https://pcdeni.github.io/CaSA/explainer/ This is tested and works inside commercial off the shelf memory with custom memory controller in the FPGA. The underlying effect is well characterized in academic papers (cmu safari, simra, dram bender, etc). In the process of getting this to work I also made previously undocumented discovery about DDR behaviour: https://pcdeni.github.io/CaSA/explainer/xor-spread.html…
- 1WB
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com
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- 3HI
I found that duplicating a specific block of 7 middle layers in Qwen2-72B, without modifying any weights, improved performance across all Open LLM Leaderboard benchmarks and took #1. As of 2026, the top 4 models on that leaderboard are still descendants. The weird finding: single-layer duplication does nothing. Too few layers, nothing. Too many, it gets worse. Only circuit-sized blocks of ~7 layers work. This suggests pretraining carves out discrete functional circuits in the layer stack that only work when preserved whole. The whole thing was developed on 2x RTX 4090s in my basement. I'm…
Mar 2026 · dnhkng.github.io
- 4SM
I wanted to see how fast an isolated code sandbox could start if I never had to boot a fresh VM. So instead of launching a new microVM per execution, I boot Firecracker once with Python and numpy already loaded, then snapshot the full VM state. Every execution after that creates a new KVM VM backed by a `MAP_PRIVATE` mapping of the snapshot memory, so Linux gives me copy-on-write pages automatically. That means each sandbox starts from an already-running Python process inside a real VM, runs the code, and exits. These are real KVM VMs, not containers: separate guest kernel, separate guest…
Mar 2026 · github.com
- 5CM
We built CodeYam Memory because Claude Code kept making the same mistakes on our codebase. Our claude.md files quickly got stale and maintaining by hand or with Claude wasn’t sufficient. While digging into this we found that Claude has a native rules system that allowed us to target specific parts of our repo with path matching. This was ideal for our use case but trying to manage these rules by hand was already not working and would be even harder with more granular, targeted rules. CodeYam Memory uses a background agent to review your coding session transcripts, identifies confusion…
Mar 2026
- 6IM
I am proud to present my solo hobby project NAND. This year-long undertaking follows the completed Nand to Tetris course, but ported to the web with its own runtime, user interface, and IDE. Using the "Load example program" selector, you can try out some programs I wrote on NAND's emulated hardware such as 2048, a genetic algorithm, and a manual stack overflow to corrupt the screen. Check out NAND at https://nand.arhan.sh Additionally, I've authored an extensive writeup about the project. Read about it on the GitHub repository's readme.
2024 · github.com
- 7AN
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com
- 8AT
A 3.16M-parameter INT4 transformer running entirely in the on-chip memory of a Xilinx Kria KV260. Zero DRAM in the token loop, 59,965 tok/s on the fabric, bit-exact. Chat with it live.
27d ago · mikeayles.com
- 9TR
built this because I got tired of re-teaching Claude Code the same context every session. Preferences, decisions, “we already tried X,” “don’t touch this file,” etc. After a few days it starts to feel like onboarding the same coworker every morning. Most “agent memory” tools auto-save everything. That feels good briefly, then memory turns into a junk drawer and retrieval gets noisy. Total Recall takes the opposite approach: a write gate. Before anything gets promoted, it asks one question: “Will this change future behavior?” If not, it doesn’t get saved. How it works: Daily log first (raw…
Feb 2026 · github.com
- 10RPRAM Prices▲241
I was inspired by this discussion https://news.ycombinator.com/item?id=39066480 about diskprices.com last month, and decided to go ahead and make a site for RAM. It's my first time building anything like this! Any tips / suggestions / calls for complete overhaul are welcome :)
2024 · ramstickprices.com
- 11AD
To try it out, simply build the project yourself from source, or use attached bootable ISO image of the system (in Releases on Github) and run it in QEMU. https://blog.vxn.dev/rou2exos-rusted-edition
2025 · github.com
- 12H1
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
2023 · sol-1.org
- 13IS
First Release is Here! I'm excited to announce the first release of i486SX_soft_FPU — a software FPU emulator for the classic Intel 486SX CPU, running on NetBSD 10! This project brings floating-point support back to life for 486SX machines, even though modern NetBSD versions no longer natively support processors without a hardware FPU. If you're into retrocomputing, operating system hacking, or just love old-school hardware, check it out! Project page: https://github.com/mezantrop/i486SX_soft_FPU Contributions, feedback, and testing are all very welcome! Let's keep these…
2025 · github.com
- 14MA
Hi HN! I'm Fischer, and I'm super stoked to share a project that I've been working on for a little over a year: Manta, an open-source, cross-platform, vendor-independent tool for debugging and rapid prototyping with FPGAs. This was originally my Master's Thesis at MIT, where I developed it for our course on FPGA design. We needed an alternative to vendor debugging tools, which only supported x86 machines running Windows or Linux. We were able to patch in macOS support with VMs, but as more students came bringing ARM-based devices, we needed a new tool. So I developed this. It's called Manta,…
2024 · fischermoseley.github.io
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- 16RG
Hey HN! I'm José, and I built Recall to solve a problem that was driving me crazy. The Problem: I use Claude for coding daily, but every conversation starts from scratch. I'd explain my architecture, coding standards, past decisions... then hit the context limit and lose everything. Next session? Start over. The Solution: Recall is an MCP (Model Context Protocol) server that gives Claude persistent memory using Redis + semantic search. Think of it as long-term memory that survives context limits and session restarts. How it works: - Claude stores important context as "memories" during…
Oct 2025 · npmjs.com
- 17EA
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com
- 18IB
I built a tiny 8-bit CPU simulator in Python to better understand how computers work at a low level. It visualizes registers, memory, and instructions in real-time, so you can actually see each operation as it happens. You can write simple assembly code and watch how the CPU executes it step by step. The project is mainly for learning and experimentation, but I’d love feedback or ideas for improvement.
Oct 2025 · github.com
- 19IM
I built ChipBuilder to make computer architecture more approachable through interactive puzzles. You start with basic logic gates like AND, OR, and NOT, then gradually combine them into adders, multiplexers, memory, an ALU, and eventually a complete CPU. Once you've built the hardware, you can write assembly programs that run on the processor you created. The game is inspired by courses like Nand2Tetris, but everything runs directly in the browser with a visual circuit editor, simulations, and progressively harder challenges.
Jul 2026 · select.supply
- 20OI
Nov 2025 · github.com
- 21IB
Built a simple web app that tells you which open-source LLMs will work on your hardware. It auto-detects your specs, shows compatible models from Hugging Face, gives realistic performance estimates (tokens/sec), and recommends quantization settings. You can also manually input specs to see "what if I upgraded my RAM?" Made this after wasting time downloading giant models only to find they crawled on my hardware. Hope it saves you some frustration!
2025 · caniusellm.com
- 22CA
Made an ARM Thumb CPU from scratch in a digital circuit simulator for fun and decided to push the joke a little further and run real stuff on it, like a Web server, a Scheme interpreter, a MIDI player, and a VT100 emulator. This is basically a how-did-we-get-here blogpost, it's my second one of this kind, I'd love any feedback you might have.
2022 · zdimension.fr
- 23IW
Facebook's Katran looked too scary (and I don't do C++), so I thought I would investigate using XDP/eBPF to redirect packets at high speed and Go to do the control plane work of health-checking backed servers and managing configuration. With luck the resulting binary should be easy to deploy by non-developers. It's still not mature, but seems to work. Code was written in a very exploratory manner, and I'm not a developer so it is quite shocking at the moment, but I aim to improve it. It is intended to be horizontally scalable with ECMP and has been tested on service providing…
2022 · github.com
- 24RP
The excitement surrounding PrismML’s 1-bit/ternary Bonsai models has the industry closely watching how smartphone giants, particularly Apple, will implement LLMs on edge devices. Moving AI on-device is a brilliant and necessary strategy. It ensures absolute user privacy in alignment with EU regulations, fundamentally shifts the economics away from costly cloud inference, and paves the way for a significant hardware upgrade supercycle as users seek true AI-capable silicon. To create a smart on-device "Semantic Router," models need to reach the 27B+ parameter scale. Achieving this on a…
Jul 2026
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