
Cold Chip Architecture
Achieving 99.9% Energy Efficiency with Non-Dissipative Logic
What it does
We solved the semiconductor "Thermal Wall." A non-dissipative logic framework achieving measured 99.9% energy recovery efficiency through 0.5nm modular reorganization.
Does the same job
all alternatives →- IMI made a discrete logic network card2024 · qdiv.dev · ▲541
- TCTernary Computer System2024 · ternary-computing.com · ▲145
Hi everyone! I'm an Italian programmer, very passionate about computer architecture. Some time ago I realized that some architectures potentially much superior to the classic VonNeumann, have been forgotten because there were no reliable technical solutions to implement them. One of these architectures particularly struck me and it is the "Dataflow architecture", in which there is no Program counter, but the instructions are executed in real contemporaneity whenever the operands are available. In trying to find a technical solution that implements this type of architecture effectively…
- ANA nibble-oriented CPU in Verilog to build a scientific calculatorMay 2026 · github.com · ▲119
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
- IBInstaPart – Build circuit boards faster with instant parts2016 · snapeda.com · ▲309
- WBWe built an 8-bit CPU as 2nd year EE studentsJun 2026 · github.com · ▲108
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
- C8CHIP-8 console implemented in FPGA2018 · github.com · ▲120
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