Alternatives
Products that do what Cold Chip Architecture does
Achieving 99.9% Energy Efficiency with Non-Dissipative Logic
- 1IM
2024 · qdiv.dev
- 2TC
Hi everyone! I'm an Italian programmer, very passionate about computer architecture. Some time ago I realized that some architectures potentially much superior to the classic VonNeumann, have been forgotten because there were no reliable technical solutions to implement them. One of these architectures particularly struck me and it is the "Dataflow architecture", in which there is no Program counter, but the instructions are executed in real contemporaneity whenever the operands are available. In trying to find a technical solution that implements this type of architecture effectively…
2024 · ternary-computing.com
- 3AN
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com
- 4IB
2016 · snapeda.com
- 5WB
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com
- 6C8
2018 · github.com
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- 10MF
2015 · github.com
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- 12MN
2020 · murex.rocks
- 13MS
2011 · github.com
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I built ChipBuilder to make computer architecture more approachable through interactive puzzles. You start with basic logic gates like AND, OR, and NOT, then gradually combine them into adders, multiplexers, memory, an ALU, and eventually a complete CPU. Once you've built the hardware, you can write assembly programs that run on the processor you created. The game is inspired by courses like Nand2Tetris, but everything runs directly in the browser with a visual circuit editor, simulations, and progressively harder challenges.
Jul 2026 · select.supply
- 15TA
2021 · joetruncale.medium.com
- 16AT
It is based on phase noise, consumes less than 60 LUT4s/FFs and achieves up to 7.99 bits of entropy per byte. Feel free to comment if you have any questions, ideas or thoughts :)
2023 · github.com
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- 18EA
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com
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- 20MC
2018 · github.com
- 21ZC
Zero-Knowledge Proofs (ZKPs) let an untrusted proved show that computation was executed correctly without revealing the inputs to the verifier. However to prove anything, the computation first has to be expressed as a circuit: a system of polynomial equations (constraints) over a finite field. Circuits are the assembly language of zk and every constraint costs prover (and sometimes verifier) time, so production circuits are aggressively hand-optimized. Over the last months, we have been experimenting with writing formal specifications instead and letting LLMs produce the circuits: as long as…
Jul 2026 · zk.golf
- 22BG
2018 · medium.com
- 23SA
Hi, everyone! I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals. In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed. SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the…
Jan 2026 · github.com
- 24NA
2018 · nanostack.io
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