Alternatives
Products that do what Photonic Logic Chip does
Interference fringes as logic gates no silicon, 5mW @ 50GHz
- 1IM
2022 · imihajlov.tk
- 2IM
2024 · qdiv.dev
- 3IM
Inspired by games like Turing Complete/Virtual Circuit Board/Logic World, I tried to make a mix of aseprite and wiredworld/wired-logic, the idea being the user can build a digital circuit using a "fullstack" pixelart creation workflow. The circuit is just an image. The primitives are (i) connected wires which have undefined, 0 or 1 state during simulation (displayed brighter or darker in function of the state) and (ii) NANDs, which are little pixel triangles. During simulation the user can interact with any wire by clicking on it, toggling its state, which is cool for messing…
2024 · github.com
- 4ZC
Zero-Knowledge Proofs (ZKPs) let an untrusted proved show that computation was executed correctly without revealing the inputs to the verifier. However to prove anything, the computation first has to be expressed as a circuit: a system of polynomial equations (constraints) over a finite field. Circuits are the assembly language of zk and every constraint costs prover (and sometimes verifier) time, so production circuits are aggressively hand-optimized. Over the last months, we have been experimenting with writing formal specifications instead and letting LLMs produce the circuits: as long as…
Jul 2026 · zk.golf
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- 8ST
We've just launched v2.5 of SatCat5, the open-source FPGA Ethernet switch [1]. SatCat5 contains various FPGA building blocks that let you build a custom mixed-media Ethernet switch. It was originally intended for cubesats [2] but has many other potential applications. The headline feature for this release is support for the IEEE-1588 Precision Time Protocol (PTP). SatCat5 has demonstrated end-to-end synchronization to within 50 ps-rms, which is approaching the world-leading performance of CERN's White Rabbit Project [3]. Except we're doing time-transfer over regular, non-synchronous…
2024 · github.com
- 9ZP
The model uses a 1024-dimensional complex Hilbert space with 32 layers of programmable Mach–Zehnder meshes (Reck architecture) and derives token probabilities directly via the Born rule. Despite using only unitary operations and no attention mechanism, a 1024×32 model achieves coherent TinyStories generation after < 1.8 hours of training on a single consumer GPU. This is Part 1 - the next step is physical implementation with $50 of optics from AliExpress.
Nov 2025 · zenodo.org
- 10FP
2021 · floptimal.com
- 11IM
This is a little toy project of mine that lets you simulate digital logic graphs. It was inspired by Minecraft's Redstone and the Piet esolang. It's got some serious drawbacks-- you write circuits as PNGs and simulate them with a Python interface. It's slow to run and slow to experiment with. And it is certainly difficult to use for people with any kind of color blindness. But despite that, I hope this can still be a fun toy!
2022 · github.com
- 12AN
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com
- 13
Interactive logic gate simulation for students and engineers
May 2026 · logicsimulation.com
- 14AI
A clock app for my Apple ][ clone in 6502 assembly, using interrupts generated by an inductive proximity sensor and a physical pendulum clock. I wanted to polish the code a bit more before sharing (I especially dislike the self modifying code part), but the computer seems to have developed a hardware problem lately and it keeps crashing (bad RAM chip most likely), so I am sharing as is.
2024 · github.com
- 15WL
2016 · github.com
- 16H1
This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.
2023 · sol-1.org
- 17
This is a poc utilizing the Burgers' viscous dissipation term While photons are not fluids, couldn't jitter be interpreted as a fluid-like phenomenon?
29d ago · github.com
- 18WB
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com
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- 20AT
It is based on phase noise, consumes less than 60 LUT4s/FFs and achieves up to 7.99 bits of entropy per byte. Feel free to comment if you have any questions, ideas or thoughts :)
2023 · github.com
- 21
A new programming language rooted in Pure Mathematics
2025
- 22QQ
Apr 2026 · github.com
- 23
- 24IM
Introducing the 3D Printed Binary Enigma (10 Enigma) – the ultimate encryption and decryption device, no batteries required! Inspired by the iconic Enigma machines of WWII, this sleek and intuitive device lets you encode and decode messages “effortlessly”. Or how else are we going to send secure messages in the future?
2024 · makerworld.com
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