Dev tools · alternatives · 2026

24 alternatives to Brainfuck to RISC-V JIT compiler written in Zig

Hi everybody, this was my project to learn Zig and RISC-V+x86_64 assembly. Not sure if anybody is actually interested in yet another Brainfuck compiler, so I'll just write up some random things I learned while building it! - A primitive assembly stitching compiler is 10x faster than the interpreter. Did not expect that. - The generated x86 code is really bad (e.g. it always uses 6 or 7 byte sized instructions with 32-bit immediates when there are much smaller ones) but it doesn't really matter. Good code generated by GCC and clang for transpiled Brainfuck->C is not much faster as it's…

Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes.

1
I wrote an OS in 1000 lines of Zig▲151
A minimal RISC-V 32-bit OS written in Zig. Contribute to botirkhaltaev/pico-os development by creating an account on GitHub.
2025 · github.com · its alternatives →
2
BrainIDE – A feature-packed Brainfuck compiler▲53
Brainfuck IDE using python, bundled with it's own compiler - LovetheFrogs/BrainIDE
2022 · github.com · its alternatives →
3
IDE for Learning RISC-V▲105
RARS -- RISC-V Assembler and Runtime Simulator. Contribute to TheThirdOne/rars development by creating an account on GitHub.
2019 · github.com · its alternatives →
4
Synesthesia – Optimizing brainfuck compiler implemented as Nim macros▲33
A (mildly) optimizing brainf*ck compiler implemented as Nim macros - Jeff-Ciesielski/synesthesia
2019 · github.com · its alternatives →
5
RISC-V core written in 600 lines of C89▲190
32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
6
I shrank DeepSeek V4 Flash to 57GB and it wrote a compiler on my Mac▲21
I built a specialized package of DeepSeek V4 Flash 0731 (originally 284B total parameters, 13B active), preserving reasoning, tool calling and coding capabilities: https://huggingface.co/steadfastgaze/DeepSeek-V4-Flash-0731-... I let it write a minimal C compiler targeting ARM64, then test the result with Fibonacci and FizzBuzz programs, and it succeeded in less than 1 hour, with the full recording at: https://youtu.be/XiwSilmV8B0 You can run it on Silicon Macs with my engine https://github.com/steadfastgaze/MoEspresso, while one of the…
Aug 2026 · huggingface.co · its alternatives →
7
A work-in-progress C compiler from scratch▲159
Programming language that compiles into a x86 ELF executable. - riicchhaarrd/ocean
2021 · github.com · its alternatives →
8
Tiny VM sandbox in C with apps in Rust, C and Zig▲196
Minimalist, dependency-free virtual machine sandbox for microcontrollers and other resource-constrained devices. Single C file, no dynamic memory allocations, asynchronous design, pure C99 - ringtailsoftware/uvm32
Dec 2025 · github.com · its alternatives →
9
Minimax – A Compressed-First, Microcoded RISC-V CPU▲171
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
10GI
Going into freshman year, figured I should build an interpreter▲138
Hi all! I'm going into my freshman year, and figured that the best way to prepare for the intro to programming Racket course would be to implement my own garbage-collected, dynamically typed, functional programming language in C ;) Anyways... here's the repo: https://github.com/liam-ilan/crumb I started learning C over the summer, so I still have a whole lot to learn... Any feedback would be greatly appreciated! :D
2023 · its alternatives →
11AR
A RISC-V core in Racket▲122
2021 · guillaume.baierouge.fr · its alternatives →
12LA
Lambduck, a Functional Programming Brainfuck▲70
What if Brainfuck was less like C and more like Scheme? The interpreter implemetation is pretty bad. It's not very fast, it's not very good, and it's probably not very correct. But maybe there's some vaguely interesting programs you could write with it! For example, the Y combinator: λf. (λx. f (x x)) (λx. f (x x)) is written as: \` \`1 `0 0 \`1 `0 0
2025 · imjakingit.github.io · its alternatives →
13
Zig Topological Sort Library for Parallel Processing▲114
I believe the best way to learn a language is by doing an in-depth project. This is my first Zig project intended for learning the ropes on publishing a Zig package. It turns out to be quite solid and performant. It might be a bit over-engineered. This little library is packed with the following features: - Building dependency graph from dependency data. - Performing topological sort on the dependency graph. - Generating dependence-free subsets for parallel processing. - Cycle detection and cycle reporting.
2025 · github.com · its alternatives →
14
Compile for Arm at native speeds in an emulated system▲63
Runs AWS graviton2 images on intel, with native-speed compile times - valkmit/aws-graviton2-on-intel
2021 · github.com · its alternatives →
15
I wrote a VM and Compiler for a small language in Go▲37
My implementation of Thorsten Bell's book (Writing an Interpreter in Go) - actuallyachraf/monkey-giggle
2020 · github.com · its alternatives →
16
Cj–tiny no-deps JIT in C for x86-64 and ARM64▲21
Hey y’all! About 7 years ago, I had this idea to write a JIT with an autogenerated backend for x86 based on the ISA specs. I sketched something out and then just kinda let it sit. I picked it up again a few weeks ago and made a complete-ish backend for both x86 and ARM64. It has no dependencies, the backends are completely autogenerated (by horrible, horrible JS scripts), and I built a small abstraciton layer for things like functions prologues etc. It’s super duper early and will probably break on your machine, but it’s good enough to compile some cool examples (look at the examples…
Nov 2025 · github.com · its alternatives →
17
RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint▲7
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
Mar 2026 · github.com · its alternatives →
18
New RISC-V emulator for Computer Science education▲71
Just released EGG, an emulator created for teaching Assembly and microprocessors (designed to suit the needs of the Microprocessors classes, at Universidade Federal do Paraná, Brazil). The emulator will support multiple architetures in the future, but currently only RISC-V is implemented.
2024 · github.com · its alternatives →
19
C++17 RISC-V RV32GC / RV64GC userspace emulator library▲31
The fastest RVA23 RISC-V sandbox. Contribute to libriscv/libriscv development by creating an account on GitHub.
2020 · github.com · its alternatives →
20
I built a RISC-V emulator that runs DOOM▲50
Demo: https://www.youtube.com/watch?v=f5uygzEmdLw Hi HN, I built a RISC-V emulator that implements the RV32IM instruction set and a minimal syscall interface to run DOOM. A few weeks ago, I got my first output with a simple hello world assembly program. Since then I have been working tirelessly to get DOOM to run. I needed to figure out how to run C programs first, and came across newlib, which allows the underlying environment to implement the syscall stubs one by one until the programs run. I have also added ELF loading, but currently only a single `PT_LOAD` segment is…
May 2026 · github.com · its alternatives →
21
A pipelined RISC-V processor written in VHDL▲65
A pipelined RISCV implementation in VHDL. Contribute to inforichland/freezing-spice development by creating an account on GitHub.
2015 · github.com · its alternatives →
22
I made a set of tools to write kernel prototypes.▲8
This is a personal project I've been working on and off for the past few years. It's a set of tools that have allowed me to prototype quickly small (and increasingly bigger) kernels, and create userspace programs to interact with them. Supports riscv64, amd64 and i386. The intel port has been tested and used on real hardware, from big dual-socket Xeon machines to an old X220. It is all C, I have plan to make rust bindings for the kernel library. But again, they're plans at this stage. Porting to new architectures is relatively simple, a basic port to riscv took me a couple of weeks of…
2024 · github.com · its alternatives →
23
A fast Brainfuck interpreter in pure Bash▲6
A heavily optimizing Brain**** interpreter written in Bash! - Gandalf-/BrainBash
2017 · github.com · its alternatives →
24ZD
Zig-DbC – A design by contract library for Zig▲46
Hi everyone, I've made an open-source library for using design by contract (DbC) principles in the Zig programming language. It's called Zig-DbC, and it currently provides the following features: - A simple API to define preconditions, postconditions, and invariants. - Contracts are active in `Debug`, `ReleaseSafe`, and `ReleaseSmall` modes to catch bugs early. - All checks are removed at compile time in `ReleaseFast` mode for zero performance cost. - An optional mode to handle partial state changes in functions that return errors. - Transparent error handling that propagates errors from…
2025 · its alternatives →

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