Dev tools · alternatives · 2026
24 alternatives to Hosted RISC-V CI/CD Runners
Job executors for CI/CD runtimes using RISC-V architecture
Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. Hosted RISC-V CI/CD Runners launched in 2024; newer entries below may have overtaken it.
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2021 · guillaume.baierouge.fr · its alternatives →
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Hi HN! My name is Marko and I am working on a CI/CD system at harmont.dev, a CI/CD system that sucks slightly less. As I've been working on the cloud, I realized that the CLI might be generally useful as a task runner, even if you don't care for our CI/CD, and that's what I'm sharing here! Every CI system I've used at Tesla, Bun, and mesa.dev has had the same problems: stateless and slow (GHA), or stateful and horizontally unscalable (Jenkins), with YAML on top of either. The straw that broke the camel's back for me was the realization that all my Claudes are waiting upwards…
May 2026 · github.com · its alternatives →
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2023 · github.com · its alternatives →
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I made this game to teach my daughter how buffer overflows work. I want her to look at programs as things she can change, and make them do whatever she wants. Building your exploit in memory and jumping to it feels so cool. I hope this game teaches kids and programmers (who seem to have forgotten what computers actually are) that its quite fun to mess with programs. We used to have that excitement few years ago, just break into softice and change a branch into a nop and ignore the serial number check, or go to a different game level because this one is too annoying. While working on the game…
2023 · punkx.org · its alternatives →
- 10WX
Hey HN, I’m Surya and I’m excited to show you WarpBuild! WarpBuild provides fast, secure `x86-64` and `arm64` Github actions runners. This speeds up your workloads by 30%, at half the cost, and takes ~2mins to get started. We’ve been seeing pretty good results since we opened up signups a week ago and I’ve shared some numbers publicly here [1]. Currently, we support linux runners for Github organizations (not personal accounts) and MacOS support is coming soon (~Jan). The way the runners work is deceptively simple: Runners are assigned to hardware that is ideal for build workloads with fast…
2023 · warpbuild.com · its alternatives →
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Modified version of the original from http://www.projectoberon.com/ for use with the Oberon IDE - GitHub - rochus-keller/OberonSystem at op2-rv32
30d ago · github.com · its alternatives →
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Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
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Hello HN, my name is Varun, and I am the co-founder of StepSecurity. Here is the backstory about Harden-Runner. We thoroughly researched past software supply chain security incidents. The devastating breaches of SolarWinds, Codecov, and others, have one thing in common – they attacked the CI/ CD pipeline or the build server. These incidents made it clear that a purpose-built security agent was needed for CI/ CD. While there are numerous agents available for desktops and servers, such as from CrowdStrike and Lacework, none have been tailored specifically to address the unique risks…
2023 · github.com · its alternatives →
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- 21MA
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →