Alternatives
Products that do what CoreTrace, a visual 16-bit CPU simulator does
I built a 16-bit CPU simulator that runs entirely in the browser. You can write assembly, run it, or step through it one instruction at a time while watching what happens inside the CPU. It shows the registers, memory, flags, ALU, buses, and datapath as the program executes. You can also set breakpoints, inspect execution cycles, replay previous cycles, and try some example programs. I built this because I wanted CPU architecture to feel more tangible. Reading about fetch, decode, registers, buses, and the ALU is one thing. Watching an instruction actually move through the CPU is much more…
- 18B
2020 · github.com
- 2H3
2016 · youtube.com
- 3CS
2015 · github.com
- 4OC
2018 · nandgame.com
- 5
- 6CA
A recent HackerNews comment - “For one programmer's hourly cost, you could run 4000 CPU cores continuously. Can there really be no practical way to apply thousands of cores to boosting the programmer's productivity?” https://news.ycombinator.com/item?id=19339467 This is what we have come up with. The current productivity tools - Slack, Asana, Trello, Facebook Workplace, etc. - are great, but lack direct access to your code. Building a tool directly around the code makes it more powerful for software developers: CoDiff. https://codiff.com The foundation of CoDiff is a…
2019
- 7IA
Hey HN, I am making an 8-Bit CPU in Logisim and blogging about it.t's nothing fancy, really simple, unoptimized dumb CPU for sake of learning. I am no electrical engineer, I am just a self-taught dude who has programming as a hobby and wanted to dive deeper into abstractions. So here it is, so far I wrote 2 parts: [links redacted] I welcome any and all critique and feedback, as I can be wrong about everything for sure.
2017
- 8MS
2011 · github.com
- 9PA
A little game I made to show off an old project. The functionality of the CPU is derived entirely from simulated logic gates. All the operations and control flow are based on the underlying properties of the logic gates, and changing their operation leads to corresponding changes in function. The original game code is all python and it runs in the browser using wasm/pyodide. Not very mobile friendly
2024 · loreley.one
- 10IM
This is a personal project I've been working on and off for the past few years. It's a set of tools that have allowed me to prototype quickly small (and increasingly bigger) kernels, and create userspace programs to interact with them. Supports riscv64, amd64 and i386. The intel port has been tested and used on real hardware, from big dual-socket Xeon machines to an old X220. It is all C, I have plan to make rust bindings for the kernel library. But again, they're plans at this stage. Porting to new architectures is relatively simple, a basic port to riscv took me a couple of weeks of…
2024 · github.com
- 11
- 12HA
Most ZK proving systems are optimized for server-grade hardware with massive RAM. When scaling to industrial-sized traces (2^20+ rows), they often hit a "Memory Wall" where allocation and data movement become a larger bottleneck than the actual computation. I have been developing Hekate, a ZK engine written in Rust that utilizes a Zero-Copy streaming model and a hybrid tiled evaluator. To test its limits, I ran a head-to-head benchmark against Binius64 on an Apple M3 Max laptop using Keccak-256. The results highlight a significant architectural divergence: At 2^15 rows: Binius64 is faster…
Jan 2026
- 13IT
2017 · youtube.com
- 14EC
I participated in the Nvidia + Vercel 2 hour hackathon in SF tonight, and built something I've wanted, but hadn't tried building. I implemented an MCP Server and VS Code extension to allow Claude Desktop to place breakpoints, step through code, and execute expressions (assuming language support). So you can ask it a question that requires actually stepping through the code and now it can actually do that - check values for you, etc. It's _definitely_ not perfect. Have improvements? Please make a PR!
2025 · github.com
- 15IE
Quick note on how it works and how I've done my batch embedding engine IgniteMS. The whole thing runs as one process using Rust, reading input, tokenizing, packing batches, keeping the queue full. TensorRT handles inference. Python is only as a wrapper. I built it this way because when you use more than couple of GPUs, the GPUs stop being the problem. CPU cannot feed them fast enough. One A100 can go through batches faster than Python can tokenize and feed, so the GPU just sits there idle waiting for work. Most of my time went into optimizing this. At 8 GPUs that was basically the entire…
Jun 2026 · github.com
- 16LS
Earlier this year, I took a month to reexamine my coding habits and rethink some past design choices. I hope to rewrite and improve my FOSS libraries this year, and I needed answers to a few questions first. Perhaps some of these questions will resonate with others in the community, too. - Are coroutines viable for high-performance work? - Should I use SIMD intrinsics for clarity or drop to assembly for easier library distribution? - Has hardware caught up with vectorized scatter/gather in AVX-512 & SVE? - How do secure enclaves & pointer tagging differ on Intel, Arm, & AMD? - What's…
2025 · github.com
- 17IB
Hey HN! Last week I was working on a website and needed a way to synchronise visuals with live music. I've used MIDI controllers for this before, but I am travelling right now and don't have mine with me. So I had the crazy idea to build a browser extension that uses the keyboard as input and includes a sequencer. I gave myself 24 to work on it. It ended up taking longer (of course), specially since I ended up creating a demo, a small landing, docs, and an intro video. Took me one week from idea to launch (pushed quite a bit tbh). Features: - Works as a browser extension. Atm distributed…
2024 · minitap.io
- 18GS
I've worked on several projects writing and implementing specifications (particularly CLN): I've found the specs I write are much better when I quote them in the implementation, so I can see what implementers need to know. Also, when specs change in development, it's almost trivial to find where to update the code. This project is a formalization of my various hacky scripts which ensure the requirements are accurately quoted, and give coverage if any are missing. Not a major Opus, but I hope someone else finds it useful!
Jul 2026 · greatspectations.org
- 19HS
Hi everyone! We (Christopher and Govind) have started a video tutorial series of 20-25 minute long episodes on how to make various common computer science data structures, such as vectors, linked lists, hashmaps, and so on. So far, we’ve done a two-part series on how to implement vectors. Links to parts one and two of the Vectors series: https://www.youtube.com/watch?v=vr0KzD_Owxc https://www.youtube.com/watch?v=t3kgbdhUIxU (Sorry about the low quality of the video in the first link, we accidentally recorded in 720p. The second part is in 1080p!) Although so far…
2019
- 20WM
Hi HN, I’ve spent the last decade building hardware products like humanoid robots, 3D printers, and self-driving tractors. I needed a tool to navigate technical documents faster, so I created one with friends. This tool helps with component search, cross-referencing, comparison, and debugging. We’d love your feedback, whether you find it useful or not. Thank you! Try it here: www.convergelab.ai
2024 · convergelab.ai
- 21RV
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD. Highlights: 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit…
Mar 2026 · github.com
- 22AP
2020 · github.com
- 23SM
I am sharing a research-grade, open-source trading execution framework that achieves a median end-to-end decision latency of 890 nanoseconds on commodity hardware. The project is designed for education, systems research, and latency instrumentation, not for live trading. It focuses on understanding exactly where every nanosecond goes in a trading execution path. Key features: - Kernel-bypass networking: Direct userspace access to NICs via custom drivers, 20-50 ns RX latency - Lock-free SPSC/MPSC queues: Zero-copy architecture - SIMD feature extraction: About 40 ns per update using…
Dec 2025 · submicro.krishnabajpai.me
- 24SA
Hi Everyone! I built this 3D desktop environment, CLI, and visualizer tool. It's in very early stages and has many updates in the pipeline. It is written in UE BP, C++, Python, and some React, Javascript, HTML, and CSS. The included videos describe plans for new features and major updates. I would appreciate any feedback on it!
2023 · github.com
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