Dev tools · alternatives · 2026

J1a is a minimal 16-bit CPU written in Verilog that runs on Lattice FPGAs using open source IceStorm tools. It fits on the iCEstick evaluation board with 8K of RAM and executes SwapForth, a complete interactive Forth… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. First ever FPGA CPU built using open source tools? launched in 2015; newer entries below may have overtaken it.

1. 1
   We built an 8-bit CPU as 2nd year EE students▲108

   Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…

   Jun 2026 · github.com · its alternatives →

2. 2
   My x86 emulator written in JavaScript▲765

   Run KolibriOS, Linux or Windows 98 in your browser

   2013 · copy.sh · its alternatives →

3. 3
   Icepi Zero – The FPGA Raspberry Pi Zero Equivalent▲233

   I've been hacking away lately, and I'm now proud to show off my newest project - The Icepi Zero! In case you don't know what an FPGA is, this phrase summarizes it perfectly: "FPGAs work like this. You don't tell them what to do, you tell them what to BE." You don't program them, but you rewrite the circuits they contain! So I've made a PCB that carries an ECP5 FPGA, and has a raspberry pi zero footprint. It also has a few improvements! Notably the 2 USB b ports are replaced with 3 USB C ports, and it has multiple LEDs. This board can output HDMI, read from a uSD, use a SDRAM and much more.…

   2025 · github.com · its alternatives →

4. 4
   CHIP-8 console implemented in FPGA▲120

   CHIP-8 console on FPGA. Contribute to pwmarcz/fpga-chip8 development by creating an account on GitHub.

   2018 · github.com · its alternatives →

5. 5
   H2 Forth CPU▲120

   A Forth CPU and System on a Chip, based on the J1, written in VHDL - howerj/forth-cpu

   2019 · github.com · its alternatives →

6. 6MA
   Manta – A tool for FPGA Debugging and Rapid Prototyping▲86

   Hi HN! I'm Fischer, and I'm super stoked to share a project that I've been working on for a little over a year: Manta, an open-source, cross-platform, vendor-independent tool for debugging and rapid prototyping with FPGAs. This was originally my Master's Thesis at MIT, where I developed it for our course on FPGA design. We needed an alternative to vendor debugging tools, which only supported x86 machines running Windows or Linux. We were able to patch in macOS support with VMs, but as more students came bringing ARM-based devices, we needed a new tool. So I developed this. It's called Manta,…

   2024 · fischermoseley.github.io · its alternatives →

7. 7
   Gameslab, a FPGA powered handheld game console▲406

   Adventures in hardware hacking, low-level software, FPGAs, and more!

   2019 · craigjb.com · its alternatives →

8. 8
   OpenRISC JavaScript emulator emulates up to 16 cores▲43

   Online OR1K Emulator running Linux. Contribute to s-macke/jor1k development by creating an account on GitHub.

   2014 · github.com · its alternatives →

9. 9H1
   Homebrew 16bit CPU from 74HC logic with C compiler and Unix-like OS▲192

   This is a 16bit CPU+Minicomputer from pure 74 series logic. It has user/kernel modes, virtual memory, prioritized IRQ's and DMA. It has a full C compiler and a unix-like OS. It's still in development.

   2023 · sol-1.org · its alternatives →

10. 10
    A nibble-oriented CPU in Verilog to build a scientific calculator▲119

    The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…

    May 2026 · github.com · its alternatives →

11. 11
    FlopperZiro – A DIY open-source Flipper Zero clone▲364

    A Flipper Zero clone, but cheapest, DIY and simply Open Source, made with Arduino IDE - lraton/FlopperZiro

    2025 · github.com · its alternatives →

12. 12AT
    A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)▲79

    A 3.16M-parameter INT4 transformer running entirely in the on-chip memory of a Xilinx Kria KV260. Zero DRAM in the token loop, 59,965 tok/s on the fabric, bit-exact. Chat with it live.

    Aug 2026 · mikeayles.com · its alternatives →

13. 13RP
    R8 Processor▲96

    2017 · hasaranga.com · its alternatives →

14. 14
    Tamagotchi P1 for FPGAs▲71

    After being thrust headfirst into FPGA development thanks to the Analogue Pocket, my first from scratch creation was a gate level implementation of the original Tamagotchi toy. The core, running on both the Analogue Pocket and MiSTer platforms, lets users re-experience the very first Tamagotchi from 1996 with accurate emulation, but modern features. The core has savestates (which is much harder to do in hardware vs software emulation), high turbo speeds (1,800x was the max clock speed I've reached so far), and more. Learning more about hardware and FPGAs is something I've wanted to do for…

    Oct 2025 · github.com · its alternatives →

15. 15
    Tiny VM sandbox in C with apps in Rust, C and Zig▲196

    Minimalist, dependency-free virtual machine sandbox for microcontrollers and other resource-constrained devices. Single C file, no dynamic memory allocations, asynchronous design, pure C99 - ringtailsoftware/uvm32

    Dec 2025 · github.com · its alternatives →

16. 16FU
    FPGA Ultrasound Imaging on a Raspberry Pi▲199

    un0rick is a open-source ultrasound project.

    2018 · un0rick.cc · its alternatives →

17. 17
    SatCat5, the open-source FPGA Ethernet switch▲190

    We've just launched v2.5 of SatCat5, the open-source FPGA Ethernet switch [1]. SatCat5 contains various FPGA building blocks that let you build a custom mixed-media Ethernet switch. It was originally intended for cubesats [2] but has many other potential applications. The headline feature for this release is support for the IEEE-1588 Precision Time Protocol (PTP). SatCat5 has demonstrated end-to-end synchronization to within 50 ps-rms, which is approaching the world-leading performance of CERN's White Rabbit Project [3]. Except we're doing time-transfer over regular, non-synchronous…

    2024 · github.com · its alternatives →

18. 18IJ
    InAccel + JFrog - Enterprise ready FPGA accelerator distribution▲7

    2019 · docs.inaccel.com · its alternatives →

19. 19
    I486SX_soft_FPU – Software FPU Emulator for NetBSD 10 on 486SX▲117

    First Release is Here! I'm excited to announce the first release of i486SX_soft_FPU — a software FPU emulator for the classic Intel 486SX CPU, running on NetBSD 10! This project brings floating-point support back to life for 486SX machines, even though modern NetBSD versions no longer natively support processors without a hardware FPU. If you're into retrocomputing, operating system hacking, or just love old-school hardware, check it out! Project page: https://github.com/mezantrop/i486SX_soft_FPU Contributions, feedback, and testing are all very welcome! Let's keep these…

    2025 · github.com · its alternatives →

20. 20
    A Modern C/C++ build tools (Simple, Fast, Cross-platform)▲89

    A cross-platform build utility based on Lua

    2019 · xmake.io · its alternatives →

21. 21
    Turbine – 16-bit CPU Architecture and Emulator built in C▲50

    Github: https://github.com/errorcodezero/turbine

    2025 · errorcodezero.dev · its alternatives →

22. 22
    Run globally distributed full-stack apps on high-performance MicroVMs▲98

    Hi HN! We’re Yann, Edouard, and Bastien from Koyeb (https://www.koyeb.com/). We’re building a platform to let you deploy full-stack apps on high-performance hardware around the world, with zero configuration. We provide a “global serverless feeling”, without the hassle of re-writing all your apps or managing k8s complexity [1]. We built Scaleway, a cloud service provider where we designed ARM servers and provided them as cloud servers. During our time there, we saw customers struggle with the same issues while trying to deploy full-stack applications and APIs resiliently. As…

    2023 · koyeb.com · its alternatives →

23. 23
    A 16-bit Forth machine written in VHDL▲80

    Yet Another Forth Core... Contribute to inforichland/yafc development by creating an account on GitHub.

    2014 · github.com · its alternatives →

24. 24
    FPGA soft-core of the Saab Viggen's 1963 airborne computer▲22

    A soft-core FPGA replica of the Saab CK37 — the world's first IC-based airborne computer, rebuilt from the original 1963 FMV maintenance manual and running a PID navigation loop in the original Q1.25 assembly. Target: OrangeCrab r0.2 (ECP5-25F) - FormerLab/ck37-core

    Mar 2026 · github.com · its alternatives →

Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →