Alternatives
Products that do what FPGA soft-core of the Saab Viggen's 1963 airborne computer does
- 1IM
Hello! I'm Byran. I spent the past ~6 months engineering a laptop from scratch. It's fully open-source on GH at: https://github.com/Hello9999901/laptop
2025 · byran.ee
- 2C8
2018 · github.com
- 3FA
As part of a little research and also some fun I decided to try my hand at seeing how small of an ESP32 board I can make with functioning WiFi.
Nov 2025 · github.com
- 4FE
2015 · excamera.com
- 5ST
We've just launched v2.5 of SatCat5, the open-source FPGA Ethernet switch [1]. SatCat5 contains various FPGA building blocks that let you build a custom mixed-media Ethernet switch. It was originally intended for cubesats [2] but has many other potential applications. The headline feature for this release is support for the IEEE-1588 Precision Time Protocol (PTP). SatCat5 has demonstrated end-to-end synchronization to within 50 ps-rms, which is approaching the world-leading performance of CERN's White Rabbit Project [3]. Except we're doing time-transfer over regular, non-synchronous…
2024 · github.com
- 6WB
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com
- 7IS
First Release is Here! I'm excited to announce the first release of i486SX_soft_FPU — a software FPU emulator for the classic Intel 486SX CPU, running on NetBSD 10! This project brings floating-point support back to life for 486SX machines, even though modern NetBSD versions no longer natively support processors without a hardware FPU. If you're into retrocomputing, operating system hacking, or just love old-school hardware, check it out! Project page: https://github.com/mezantrop/i486SX_soft_FPU Contributions, feedback, and testing are all very welcome! Let's keep these…
2025 · github.com
- 8TP
After being thrust headfirst into FPGA development thanks to the Analogue Pocket, my first from scratch creation was a gate level implementation of the original Tamagotchi toy. The core, running on both the Analogue Pocket and MiSTer platforms, lets users re-experience the very first Tamagotchi from 1996 with accurate emulation, but modern features. The core has savestates (which is much harder to do in hardware vs software emulation), high turbo speeds (1,800x was the max clock speed I've reached so far), and more. Learning more about hardware and FPGAs is something I've wanted to do for…
Oct 2025 · github.com
- 9CC
Dear HN community! Looking forward to hearing your feedback on ACE (assured confidential execution), technology that implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware. We target high-assurance systems that can benefit from compartmentalization and hardware-backed isolation. The key ingredient called security monitor (firmware) is implemented in Rust. The formal specification is defined as annotations directly in code and gets translated to Coq using RefinedRust automation. ACE design is now part of the…
2025 · github.com
- 10GB
Hey HN, Over the past ~1.5 years, I built an open-source FPGA retro emulation handheld that can play Game Boy, Game Boy Color, and Game Boy Advance cartridges. To my knowledge, there isn't an existing open-source FPGA emulator that can play physical cartridges like this. One of my main goals was to do all of the pieces myself, and be able to understand every component of it, so I designed my own PCB, wrote the firmware, wrote a Game Boy and Game Boy Advance emulator for the FPGA (using the Chisel HDL), and designed a 3D-printed case. I detailed the design and development process in the…
2025 · eli.lipsitz.net
- 11IZ
I've been hacking away lately, and I'm now proud to show off my newest project - The Icepi Zero! In case you don't know what an FPGA is, this phrase summarizes it perfectly: "FPGAs work like this. You don't tell them what to do, you tell them what to BE." You don't program them, but you rewrite the circuits they contain! So I've made a PCB that carries an ECP5 FPGA, and has a raspberry pi zero footprint. It also has a few improvements! Notably the 2 USB b ports are replaced with 3 USB C ports, and it has multiple LEDs. This board can output HDMI, read from a uSD, use a SDRAM and much more.…
2025 · github.com
- 12
- 13IB
A while back I wrote a CHIP-8 emulator (which is considered the Hello, World! of emulators and is more accurately a virtual machine since historically CHIP-8 was an interpreted language running on top of the COSMAC VIP to make game programming easier). But a few months ago I got really interested in embedded software, so decided it would be neat to port my emulator to a STM32 MCU and design a console around it as a learning experience, since CHIP-8 never existed as a physical system. I didn't know much about embedded software when I began, and even less about electronics, but I managed to…
2022 · github.com
- 14
- 15AD
To try it out, simply build the project yourself from source, or use attached bootable ISO image of the system (in Releases on Github) and run it in QEMU. https://blog.vxn.dev/rou2exos-rusted-edition
2025 · github.com
- 16CX
2020 · github.com
- 17RW
2021 · unsafeperform.io
- 18OS
2020 · github.com
- 19EA
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com
- 20IB
We wanted to do something very challenging to prove to ourselves that we can do anything we put our mind to. The reasoning for why we chose to build a toy TPU specifically is fairly simple: - Building a chip for ML workloads seemed cool - There was no well-documented open source repo for an ML accelerator that performed both inference and training None of us have real professional experience in hardware design, which, in a way, made the TPU even more appealing since we weren't able to estimate exactly how difficult it would be. As we worked on the initial stages of this project, we…
2025 · tinytpu.com
- 21MA
Hi HN! I'm Fischer, and I'm super stoked to share a project that I've been working on for a little over a year: Manta, an open-source, cross-platform, vendor-independent tool for debugging and rapid prototyping with FPGAs. This was originally my Master's Thesis at MIT, where I developed it for our course on FPGA design. We needed an alternative to vendor debugging tools, which only supported x86 machines running Windows or Linux. We were able to patch in macOS support with VMs, but as more students came bringing ARM-based devices, we needed a new tool. So I developed this. It's called Manta,…
2024 · fischermoseley.github.io
- 22
We've been building open source embedded ADS-B receivers for a while, and spent the past 8 months smallifying our existing receiver tech with a new chip from Semtech. Ask me anything about ADSB or hardware manufacturing!
11d ago · pantsforbirds.com
- 23AV
2017 · github.com
- 24AN
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com
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