Life & fun · alternatives · 2026
24 alternatives to R8 Processor
R8 Processor is an experimental 8-bit CISC processor designed in Verilog using behavioral modeling. The hardware has been synthesized and tested on Altera FPGAs, specifically the WXEDA v2 and WaveShare Core EP4CE6… Below are 24 products that do a similar job, ranked by how close each is in meaning and then by launch-day votes. R8 Processor launched in 2017; newer entries below may have overtaken it.
- 1
Verilog2factorio▲313This project will compile verilog (a hardware description language) into factorio blueprints. - Redcrafter/verilog2factorio
2021 · github.com · its alternatives →
- 2
Run KolibriOS, Linux or Windows 98 in your browser
2013 · copy.sh · its alternatives →
- 3
CHIP-8 console on FPGA. Contribute to pwmarcz/fpga-chip8 development by creating an account on GitHub.
2018 · github.com · its alternatives →
- 4
Hi everyone, I built PyXL — a hardware processor that executes a custom assembly generated from Python programs, without using a traditional interpreter or virtual machine. It compiles Python -> CPython Bytecode -> Instruction set designed for direct hardware execution. I’m sharing an early benchmark: a GPIO test where PyXL achieves a 480ns round-trip toggle — compared to 14-25 micro seconds on a MicroPython Pyboard - even though PyXL runs at a lower clock (100MHz vs. 168MHz). The design is stack-based, fully pipelined, and preserves Python's dynamic typing without static type restrictions.…
2025 · runpyxl.com · its alternatives →
- 5
A digital logic simulation written in C. Contribute to rzscheck/logic development by creating an account on GitHub.
2020 · github.com · its alternatives →
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32-bit RISC-V CPU in ~800 lines of C89. Contribute to mnurzia/rv development by creating an account on GitHub.
2023 · github.com · its alternatives →
- 7
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch. The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable. What the project covers: - Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a…
May 2026 · github.com · its alternatives →
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GitLab Community Edition
2014 · gitlab.brokenpipe.de · its alternatives →
- 9
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs. key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers Hardwired control unit built entirely from AND/OR gate logic matrix Dual-phase clocking to eliminate race conditions Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional…
Jun 2026 · github.com · its alternatives →
- 10
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it…
Jan 2026 · github.com · its alternatives →
- 11AR
2021 · guillaume.baierouge.fr · its alternatives →
- 12MI
2025 · carimbo.run · its alternatives →
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Github: https://github.com/errorcodezero/turbine
2025 · errorcodezero.dev · its alternatives →
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DAN64 is a open software and open hardware project to build an 8-bit microcomputer using an AVR microcontroller.
2015 · usebox.net · its alternatives →
- 15AT
A 3.16M-parameter INT4 transformer running entirely in the on-chip memory of a Xilinx Kria KV260. Zero DRAM in the token loop, 59,965 tok/s on the fabric, bit-exact. Chat with it live.
Aug 2026 · mikeayles.com · its alternatives →
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I built a tiny 8-bit CPU simulator in Python to better understand how computers work at a low level. It visualizes registers, memory, and instructions in real-time, so you can actually see each operation as it happens. You can write simple assembly code and watch how the CPU executes it step by step. The project is mainly for learning and experimentation, but I’d love feedback or ideas for improvement.
Oct 2025 · github.com · its alternatives →
- 17QA
2017 · anchovieshat.github.io · its alternatives →
- 18
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and "mop up" any RV32I instructions that aren't convenient via a microcode layer? What architectural optimizations are unlocked as a result? "Minimax" is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any…
2022 · github.com · its alternatives →
- 19
Real-time YOLOv8n UAV detection on the RK3588S NPU | saturates the sensor at 46 FPS | ~140 MB RAM | fully hardware-accelerated (ISP+RGA+NPU) | on-device LLM scene summaries - alebal123bal/khadas_yolov8n_multithread
Jun 2026 · github.com · its alternatives →
- 20
World’s fastest AI chip with whopping 4 trillion transistors
2024 · cerebras.ai · its alternatives →
- 21
2015 · github.com · its alternatives →
- 22
Hi HN, To truly understand how operating systems and network protocols work, I decided to combine two classic learning tools: the xv6 teaching OS and a from-scratch TCP/IP stack. I'm excited to share the result: my own from-scratch TCP/IP networking stack running directly inside the xv6-riscv (https://github.com/pandax381/xv6-riscv-net) kernel. The project uses a modern virtio-net driver, allowing it to run seamlessly in QEMU and communicate with the host machine. Key features: - From-Scratch Stack: The core is powered by microps…
2025 · github.com · its alternatives →
- 23OA
A lightweight engine for durable execution / deterministic workflows I built with Rust, wasmtime and the WASM Component Model. Its main use is running reliable, long-running workflows that can automatically resume after failures. Looking for feedback on the approach and potential use cases!
2025 · obeli.sk · its alternatives →
- 24FE
2015 · excamera.com · its alternatives →
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Ranked by how close each launch is in meaning, then by votes. Prices were read from each product’s own site when checked and can change. Refine with your own description →